[rtsan] Add fork/execve interceptors (#117198)
[llvm-project.git] / llvm / test / TableGen / GlobalISelCombinerEmitter / match-table-miflags.td
blob24864e8aef45690ffc48fc4b31721534ecd016da
1 // RUN: llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \
2 // RUN:     -combiners=MyCombiner %s | \
3 // RUN: FileCheck %s
5 include "llvm/Target/Target.td"
6 include "llvm/Target/GlobalISel/Combine.td"
8 def MyTargetISA : InstrInfo;
9 def MyTarget : Target { let InstructionSet = MyTargetISA; }
11 def MIFlagsTest : GICombineRule<
12   (defs root:$dst),
13   (match (G_SEXT $dst, $tmp), (G_ZEXT $tmp, $src, (MIFlags FmReassoc, FmNsz, (not FmNoNans, FmArcp))):$mi),
14   (apply (G_MUL $dst, $src, $src, (MIFlags $mi, FmReassoc, (not FmNsz, FmArcp))))>;
16 def MyCombiner: GICombiner<"GenMyCombiner", [MIFlagsTest]>;
18 // CHECK:      const uint8_t *GenMyCombiner::getMatchTable() const {
19 // CHECK-NEXT:   constexpr static uint8_t MatchTable0[] = {
20 // CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(63), // Rule ID 0 //
21 // CHECK-NEXT:       GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled),
22 // CHECK-NEXT:       GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SEXT),
23 // CHECK-NEXT:       // MIs[0] dst
24 // CHECK-NEXT:       // No operand predicates
25 // CHECK-NEXT:       // MIs[0] tmp
26 // CHECK-NEXT:       GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27 // CHECK-NEXT:       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
28 // CHECK-NEXT:       GIM_MIFlags, /*MI*/1, GIMT_Encode4(MachineInstr::FmNsz | MachineInstr::FmReassoc),
29 // CHECK-NEXT:       GIM_MIFlagsNot, /*MI*/1, GIMT_Encode4(MachineInstr::FmArcp | MachineInstr::FmNoNans),
30 // CHECK-NEXT:       // MIs[1] src
31 // CHECK-NEXT:       // No operand predicates
32 // CHECK-NEXT:       GIM_CheckIsSafeToFold, /*NumInsns*/1,
33 // CHECK-NEXT:       // Combiner Rule #0: MIFlagsTest
34 // CHECK-NEXT:       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_MUL),
35 // CHECK-NEXT:       GIR_RootToRootCopy, /*OpIdx*/0, // dst
36 // CHECK-NEXT:       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
37 // CHECK-NEXT:       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
38 // CHECK-NEXT:       GIR_CopyMIFlags, /*InsnID*/0, /*OldInsnID*/1,
39 // CHECK-NEXT:       GIR_SetMIFlags, /*InsnID*/0, GIMT_Encode4(MachineInstr::FmReassoc),
40 // CHECK-NEXT:       GIR_UnsetMIFlags, /*InsnID*/0, GIMT_Encode4(MachineInstr::FmNsz | MachineInstr::FmArcp),
41 // CHECK-NEXT:       GIR_EraseRootFromParent_Done,
42 // CHECK-NEXT:     // Label 0: @63
43 // CHECK-NEXT:     GIM_Reject,
44 // CHECK-NEXT:     };
45 // CHECK-NEXT:   return MatchTable0;
46 // CHECK-NEXT: }