AMDGPU: Allow f16/bf16 for DS_READ_TR16_B64 gfx950 builtins (#118297)
[llvm-project.git] / llvm / test / TableGen / GlobalISelEmitter-notype-output-pattern.td
blob622d7fa1f7955ccf9d29b9d48c0284e331035241
1 // RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s | FileCheck %s
3 include "llvm/Target/Target.td"
4 include "GlobalISelEmitterCommon.td"
6 // CHECK:      constexpr static uint8_t MatchTable0[] = {
7 // CHECK-NEXT:   GIM_Try,
8 // CHECK-NEXT:     GIM_CheckOpcode{{.*}}GIMT_Encode2(TargetOpcode::G_ANYEXT),
9 // CHECK-NEXT:     GIM_RootCheckType{{.*}}/*Type*/GILLT_s32,
10 // CHECK-NEXT:     GIM_RootCheckType{{.*}}/*Type*/GILLT_s8,
11 // CHECK-NEXT:     GIM_RootCheckRegBankForClass{{.*}}/*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
12 // CHECK-NEXT:     // (anyext:{{.*}}=>{{.*}}(SELECT_I4:
13 // CHECK:          GIR_EraseRootFromParent_Done,
14 // CHECK-NEXT:   // Label 0:
15 // CHECK-NEXT:   GIM_Reject,
16 // CHECK-NEXT:   };
18 def SELECT_I4 : I<(outs GPR32:$dst), (ins GPR8:$cond, GPR32:$T, GPR32:$F), []>;
19 def LI : I<(outs GPR32:$dst), (ins i32imm:$src), []>;
21 def : Pat<(i32 (anyext i8:$in)), (SELECT_I4 $in, (LI 1), (LI 0))>;