llvm/test/TableGen/GlobalISelEmitter-zero-reg.td

   1 // RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
   2
   3 include "llvm/Target/Target.td"
   4 include "GlobalISelEmitterCommon.td"
   5
   6 def P0 : Register<"p0"> { let Namespace = "MyTarget"; }
   7 def PR32 : RegisterClass<"MyTarget", [i32], 32, (add P0)>;
   8 def PR32Op : RegisterOperand<PR32>;
   9
  10 def pred : PredicateOperand<OtherVT,
  11                             (ops PR32:$FR),
  12                             (ops (i32 zero_reg))> {}
  13 class PredI<dag OOps, dag IOps, list<dag> Pat>
  14   : Instruction {
  15   let Namespace = "MyTarget";
  16   let OutOperandList = OOps;
  17   let InOperandList = !con(IOps, (ins pred:$pred));
  18   let Pattern = Pat;
  19 }
  20
  21 def INST : PredI<(outs GPR32:$dst), (ins GPR32:$src), []>;
  22
  23 // CHECK: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
  24 // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_LOAD),
  25 // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
  26 // CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
  27 // CHECK-NEXT: // MIs[0] DstI[dst]
  28 // CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
  29 // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
  30 // CHECK-NEXT: // MIs[0] src
  31 // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
  32 // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
  33 // CHECK-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (INST:{ *:[i32] } GPR32:{ *:[i32] }:$src)
  34 // CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::INST),
  35 // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
  36 // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src
  37 // CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
  38 // CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
  39 // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
  40 // CHECK-NEXT: // GIR_Coverage
  41 // CHECK-NEXT: GIR_EraseRootFromParent_Done,
  42 def : Pat<(i32 (load GPR32:$src)),
  43           (INST GPR32:$src)>;