llvm/test/TableGen/GlobalISelEmitter/dead-def.td

   1 // RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false \
   2 // RUN:   -I %p/../../../include -I %p/../Common %s | FileCheck %s
   3
   4 include "llvm/Target/Target.td"
   5 include "GlobalISelEmitterCommon.td"
   6
   7 // Check that $same_name from I2 isn't copied to the root instruction.
   8
   9 def I1 : I<(outs GPR32:$same_name), (ins GPR32:$rs), []>;
  10 def I2 : I<(outs GPR32:$other_name, GPR32:$same_name), (ins GPR32:$rs), []>;
  11
  12 def : Pat<(abs i32:$x), (I1 (I2 $x))>;
  13
  14 // CHECK-LABEL: // (abs:{ *:[i32] } i32:{ *:[i32] }:$x)  =>  (I1:{ *:[i32] } (I2:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$x))
  15 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
  16 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
  17 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::I2),
  18 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
  19 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
  20 // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // x
  21 // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
  22 // CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::I1),
  23 // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[same_name]
  24 // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
  25 // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
  26 // CHECK-NEXT: // GIR_Coverage, 0,
  27 // CHECK-NEXT: GIR_EraseRootFromParent_Done,