llvm/test/TableGen/gisel-physreg-input.td

   1 // RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
   2
   3 include "llvm/Target/Target.td"
   4
   5 def TestTargetInstrInfo : InstrInfo;
   6
   7 def TestTarget : Target {
   8   let InstructionSet = TestTargetInstrInfo;
   9 }
  10
  11 def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
  12 def SPECIAL : Register<"special"> { let Namespace = "MyTarget"; }
  13 def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
  14 def Special32 : RegisterClass<"MyTarget", [i32], 32, (add SPECIAL)>;
  15
  16
  17 class I<dag OOps, dag IOps, list<dag> Pat>
  18   : Instruction {
  19   let Namespace = "MyTarget";
  20   let OutOperandList = OOps;
  21   let InOperandList = IOps;
  22   let Pattern = Pat;
  23 }
  24
  25 // Try a normal physical register use.
  26
  27 // GISEL: GIM_Try,
  28 // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
  29 // GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD),
  30 // GISEL-NEXT: // MIs[0] DstI[dst]
  31 // GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
  32 // GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
  33 // GISEL-NEXT: // MIs[0] src0
  34 // GISEL-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
  35 // GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
  36 // GISEL-NEXT: // MIs[0] Operand 2
  37 // GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
  38 // GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID),
  39 // GISEL-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src0, SPECIAL:{ *:[i32] })  =>  (ADD_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$src0)
  40 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
  41 // GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
  42 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL
  43 // GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ADD_PHYS),
  44 // GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
  45 // GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0
  46 // GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
  47 // GISEL-NEXT: // GIR_Coverage, 0,
  48 // GISEL-NEXT: GIR_EraseRootFromParent_Done,
  49 def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
  50     [(set GPR32:$dst, (add GPR32:$src0, SPECIAL))]> {
  51   let Uses = [SPECIAL];
  52 }
  53
  54 // Try using the name of the physreg in another operand.
  55
  56 // GISEL: GIM_Try,
  57 // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
  58 // GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL),
  59 // GISEL-NEXT: // MIs[0] DstI[dst]
  60 // GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
  61 // GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
  62 // GISEL-NEXT: // MIs[0] SPECIAL
  63 // GISEL-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
  64 // GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
  65 // GISEL-NEXT: // MIs[0] Operand 2
  66 // GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
  67 // GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID),
  68 // GISEL-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL, SPECIAL:{ *:[i32] })  =>  (MUL_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL)
  69 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
  70 // GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
  71 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL
  72 // GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MUL_PHYS),
  73 // GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
  74 // GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // SPECIAL
  75 // GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
  76 // GISEL-NEXT: // GIR_Coverage, 1,
  77 // GISEL-NEXT: GIR_EraseRootFromParent_Done,
  78 def MUL_PHYS : I<(outs GPR32:$dst), (ins GPR32:$SPECIAL),
  79     [(set GPR32:$dst, (mul GPR32:$SPECIAL, SPECIAL))]> {
  80   let Uses = [SPECIAL];
  81 }
  82
  83 // Try giving the physical operand a name
  84 // def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
  85 //     [(set GPR32:$dst, (add GPR32:$src0, SPECIAL:$special))]> {
  86 //   let Uses = [SPECIAL];
  87 // }