| blob | e79bb465563e84b378f261b6480cdbb4d22e3bc3 |
1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
3 ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-each -atomic-expand %s | FileCheck -check-prefix=GFX90A %s
4 ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-each -atomic-expand %s | FileCheck -check-prefix=GFX1100 %s
6 ; Contains a variety of tests with different types of atomic expansions to check that MMRAs are
7 ; preserved.
9 define i16 @test_atomicrmw_xchg_i16_global_agent(ptr addrspace(1) %ptr, i16 %value) {
10 ; GFX90A-LABEL: define i16 @test_atomicrmw_xchg_i16_global_agent(
11 ; GFX90A-SAME: ptr addrspace(1) [[PTR:%.*]], i16 [[VALUE:%.*]]) #[[ATTR0:[0-9]+]] {
12 ; GFX90A-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR]], i64 -4)
13 ; GFX90A-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
14 ; GFX90A-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
15 ; GFX90A-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
16 ; GFX90A-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
17 ; GFX90A-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
18 ; GFX90A-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
19 ; GFX90A-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE]] to i32
20 ; GFX90A-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
21 ; GFX90A-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4, !mmra [[META0:![0-9]+]]
22 ; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]]
23 ; GFX90A: atomicrmw.start:
24 ; GFX90A-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
25 ; GFX90A-NEXT: [[TMP5:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
26 ; GFX90A-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[VALOPERAND_SHIFTED]]
27 ; GFX90A-NEXT: [[TMP7:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP6]] syncscope("agent") seq_cst seq_cst, align 4, !mmra [[META0]]
28 ; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1
29 ; GFX90A-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0
30 ; GFX90A-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
31 ; GFX90A: atomicrmw.end:
32 ; GFX90A-NEXT: [[SHIFTED:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]]
33 ; GFX90A-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16
34 ; GFX90A-NEXT: ret i16 [[EXTRACTED]]
35 ;
36 ; GFX1100-LABEL: define i16 @test_atomicrmw_xchg_i16_global_agent(
37 ; GFX1100-SAME: ptr addrspace(1) [[PTR:%.*]], i16 [[VALUE:%.*]]) #[[ATTR0:[0-9]+]] {
38 ; GFX1100-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR]], i64 -4)
39 ; GFX1100-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
40 ; GFX1100-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
41 ; GFX1100-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
42 ; GFX1100-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
43 ; GFX1100-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
44 ; GFX1100-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
45 ; GFX1100-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE]] to i32
46 ; GFX1100-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
47 ; GFX1100-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4, !mmra [[META0:![0-9]+]]
48 ; GFX1100-NEXT: br label [[ATOMICRMW_START:%.*]]
49 ; GFX1100: atomicrmw.start:
50 ; GFX1100-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
51 ; GFX1100-NEXT: [[TMP5:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
52 ; GFX1100-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[VALOPERAND_SHIFTED]]
53 ; GFX1100-NEXT: [[TMP7:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP6]] syncscope("agent") seq_cst seq_cst, align 4, !mmra [[META0]]
54 ; GFX1100-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1
55 ; GFX1100-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0
56 ; GFX1100-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
57 ; GFX1100: atomicrmw.end:
58 ; GFX1100-NEXT: [[SHIFTED:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]]
59 ; GFX1100-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16
60 ; GFX1100-NEXT: ret i16 [[EXTRACTED]]
61 ;
62 %res = atomicrmw xchg ptr addrspace(1) %ptr, i16 %value syncscope("agent") seq_cst, !mmra !2
63 ret i16 %res
64 }
66 define i16 @test_cmpxchg_i16_global_agent_align4(ptr addrspace(1) %out, i16 %in, i16 %old) {
67 ; GFX90A-LABEL: define i16 @test_cmpxchg_i16_global_agent_align4(
68 ; GFX90A-SAME: ptr addrspace(1) [[OUT:%.*]], i16 [[IN:%.*]], i16 [[OLD:%.*]]) #[[ATTR0]] {
69 ; GFX90A-NEXT: [[GEP:%.*]] = getelementptr i16, ptr addrspace(1) [[OUT]], i64 4
70 ; GFX90A-NEXT: [[TMP1:%.*]] = zext i16 [[IN]] to i32
71 ; GFX90A-NEXT: [[TMP2:%.*]] = zext i16 [[OLD]] to i32
72 ; GFX90A-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4, !mmra [[META0]]
73 ; GFX90A-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], -65536
74 ; GFX90A-NEXT: br label [[PARTWORD_CMPXCHG_LOOP:%.*]]
75 ; GFX90A: partword.cmpxchg.loop:
76 ; GFX90A-NEXT: [[TMP5:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[TMP11:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ]
77 ; GFX90A-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[TMP1]]
78 ; GFX90A-NEXT: [[TMP7:%.*]] = or i32 [[TMP5]], [[TMP2]]
79 ; GFX90A-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[GEP]], i32 [[TMP7]], i32 [[TMP6]] seq_cst seq_cst, align 4, !mmra [[META0]]
80 ; GFX90A-NEXT: [[TMP9:%.*]] = extractvalue { i32, i1 } [[TMP8]], 0
81 ; GFX90A-NEXT: [[TMP10:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1
82 ; GFX90A-NEXT: br i1 [[TMP10]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]]
83 ; GFX90A: partword.cmpxchg.failure:
84 ; GFX90A-NEXT: [[TMP11]] = and i32 [[TMP9]], -65536
85 ; GFX90A-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP5]], [[TMP11]]
86 ; GFX90A-NEXT: br i1 [[TMP12]], label [[PARTWORD_CMPXCHG_LOOP]], label [[PARTWORD_CMPXCHG_END]]
87 ; GFX90A: partword.cmpxchg.end:
88 ; GFX90A-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[TMP9]] to i16
89 ; GFX90A-NEXT: [[TMP13:%.*]] = insertvalue { i16, i1 } poison, i16 [[EXTRACTED]], 0
90 ; GFX90A-NEXT: [[TMP14:%.*]] = insertvalue { i16, i1 } [[TMP13]], i1 [[TMP10]], 1
91 ; GFX90A-NEXT: [[EXTRACT:%.*]] = extractvalue { i16, i1 } [[TMP14]], 0
92 ; GFX90A-NEXT: ret i16 [[EXTRACT]]
93 ;
94 ; GFX1100-LABEL: define i16 @test_cmpxchg_i16_global_agent_align4(
95 ; GFX1100-SAME: ptr addrspace(1) [[OUT:%.*]], i16 [[IN:%.*]], i16 [[OLD:%.*]]) #[[ATTR0]] {
96 ; GFX1100-NEXT: [[GEP:%.*]] = getelementptr i16, ptr addrspace(1) [[OUT]], i64 4
97 ; GFX1100-NEXT: [[TMP1:%.*]] = zext i16 [[IN]] to i32
98 ; GFX1100-NEXT: [[TMP2:%.*]] = zext i16 [[OLD]] to i32
99 ; GFX1100-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4, !mmra [[META0]]
100 ; GFX1100-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], -65536
101 ; GFX1100-NEXT: br label [[PARTWORD_CMPXCHG_LOOP:%.*]]
102 ; GFX1100: partword.cmpxchg.loop:
103 ; GFX1100-NEXT: [[TMP5:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[TMP11:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ]
104 ; GFX1100-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[TMP1]]
105 ; GFX1100-NEXT: [[TMP7:%.*]] = or i32 [[TMP5]], [[TMP2]]
106 ; GFX1100-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[GEP]], i32 [[TMP7]], i32 [[TMP6]] seq_cst seq_cst, align 4, !mmra [[META0]]
107 ; GFX1100-NEXT: [[TMP9:%.*]] = extractvalue { i32, i1 } [[TMP8]], 0
108 ; GFX1100-NEXT: [[TMP10:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1
109 ; GFX1100-NEXT: br i1 [[TMP10]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]]
110 ; GFX1100: partword.cmpxchg.failure:
111 ; GFX1100-NEXT: [[TMP11]] = and i32 [[TMP9]], -65536
112 ; GFX1100-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP5]], [[TMP11]]
113 ; GFX1100-NEXT: br i1 [[TMP12]], label [[PARTWORD_CMPXCHG_LOOP]], label [[PARTWORD_CMPXCHG_END]]
114 ; GFX1100: partword.cmpxchg.end:
115 ; GFX1100-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[TMP9]] to i16
116 ; GFX1100-NEXT: [[TMP13:%.*]] = insertvalue { i16, i1 } poison, i16 [[EXTRACTED]], 0
117 ; GFX1100-NEXT: [[TMP14:%.*]] = insertvalue { i16, i1 } [[TMP13]], i1 [[TMP10]], 1
118 ; GFX1100-NEXT: [[EXTRACT:%.*]] = extractvalue { i16, i1 } [[TMP14]], 0
119 ; GFX1100-NEXT: ret i16 [[EXTRACT]]
120 ;
121 %gep = getelementptr i16, ptr addrspace(1) %out, i64 4
122 %res = cmpxchg ptr addrspace(1) %gep, i16 %old, i16 %in seq_cst seq_cst, align 4, !mmra !2
123 %extract = extractvalue {i16, i1} %res, 0
124 ret i16 %extract
125 }
127 define void @syncscope_workgroup_nortn(ptr %addr, float %val) {
128 ; GFX90A-LABEL: define void @syncscope_workgroup_nortn(
129 ; GFX90A-SAME: ptr [[ADDR:%.*]], float [[VAL:%.*]]) #[[ATTR0]] {
130 ; GFX90A-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[ADDR]])
131 ; GFX90A-NEXT: br i1 [[IS_SHARED]], label [[ATOMICRMW_SHARED:%.*]], label [[ATOMICRMW_CHECK_PRIVATE:%.*]]
132 ; GFX90A: atomicrmw.shared:
133 ; GFX90A-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(3)
134 ; GFX90A-NEXT: [[TMP2:%.*]] = atomicrmw fadd ptr addrspace(3) [[TMP1]], float [[VAL]] syncscope("workgroup") seq_cst, align 4, !mmra [[META0]], !amdgpu.no.fine.grained.memory [[META3:![0-9]+]], !amdgpu.ignore.denormal.mode [[META3]]
135 ; GFX90A-NEXT: br label [[ATOMICRMW_PHI:%.*]]
136 ; GFX90A: atomicrmw.check.private:
137 ; GFX90A-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[ADDR]])
138 ; GFX90A-NEXT: br i1 [[IS_PRIVATE]], label [[ATOMICRMW_PRIVATE:%.*]], label [[ATOMICRMW_GLOBAL:%.*]]
139 ; GFX90A: atomicrmw.private:
140 ; GFX90A-NEXT: [[TMP3:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(5)
141 ; GFX90A-NEXT: [[LOADED_PRIVATE:%.*]] = load float, ptr addrspace(5) [[TMP3]], align 4
142 ; GFX90A-NEXT: [[VAL_NEW:%.*]] = fadd float [[LOADED_PRIVATE]], [[VAL]]
143 ; GFX90A-NEXT: store float [[VAL_NEW]], ptr addrspace(5) [[TMP3]], align 4
144 ; GFX90A-NEXT: br label [[ATOMICRMW_PHI]]
145 ; GFX90A: atomicrmw.global:
146 ; GFX90A-NEXT: [[TMP4:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(1)
147 ; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[TMP4]], float [[VAL]] syncscope("workgroup") seq_cst, align 4, !mmra [[META0]], !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.ignore.denormal.mode [[META3]]
148 ; GFX90A-NEXT: br label [[ATOMICRMW_PHI]]
149 ; GFX90A: atomicrmw.phi:
150 ; GFX90A-NEXT: br label [[ATOMICRMW_END:%.*]]
151 ; GFX90A: atomicrmw.end:
152 ; GFX90A-NEXT: ret void
153 ;
154 ; GFX1100-LABEL: define void @syncscope_workgroup_nortn(
155 ; GFX1100-SAME: ptr [[ADDR:%.*]], float [[VAL:%.*]]) #[[ATTR0]] {
156 ; GFX1100-NEXT: [[RES:%.*]] = atomicrmw fadd ptr [[ADDR]], float [[VAL]] syncscope("workgroup") seq_cst, align 4, !mmra [[META0]], !amdgpu.no.fine.grained.memory [[META3:![0-9]+]], !amdgpu.ignore.denormal.mode [[META3]]
157 ; GFX1100-NEXT: ret void
158 ;
159 %res = atomicrmw fadd ptr %addr, float %val syncscope("workgroup") seq_cst, !mmra !2, !amdgpu.no.fine.grained.memory !3, !amdgpu.ignore.denormal.mode !3
160 ret void
161 }
163 define i32 @atomic_load_global_align1(ptr addrspace(1) %ptr) {
164 ; GFX90A-LABEL: define i32 @atomic_load_global_align1(
165 ; GFX90A-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] {
166 ; GFX90A-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr
167 ; GFX90A-NEXT: [[TMP2:%.*]] = alloca i32, align 4, addrspace(5)
168 ; GFX90A-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP2]])
169 ; GFX90A-NEXT: call void @__atomic_load(i64 4, ptr [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5)
170 ; GFX90A-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(5) [[TMP2]], align 4
171 ; GFX90A-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP2]])
172 ; GFX90A-NEXT: ret i32 [[TMP3]]
173 ;
174 ; GFX1100-LABEL: define i32 @atomic_load_global_align1(
175 ; GFX1100-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] {
176 ; GFX1100-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr
177 ; GFX1100-NEXT: [[TMP2:%.*]] = alloca i32, align 4, addrspace(5)
178 ; GFX1100-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP2]])
179 ; GFX1100-NEXT: call void @__atomic_load(i64 4, ptr [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5)
180 ; GFX1100-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(5) [[TMP2]], align 4
181 ; GFX1100-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP2]])
182 ; GFX1100-NEXT: ret i32 [[TMP3]]
183 ;
184 %val = load atomic i32, ptr addrspace(1) %ptr seq_cst, align 1, !mmra !2
185 ret i32 %val
186 }
188 !0 = !{!"foo", !"bar"}
189 !1 = !{!"bux", !"baz"}
190 !2 = !{!0, !1}
191 !3 = !{}
192 ;.
193 ; GFX90A: [[META0]] = !{[[META1:![0-9]+]], [[META2:![0-9]+]]}
194 ; GFX90A: [[META1]] = !{!"foo", !"bar"}
195 ; GFX90A: [[META2]] = !{!"bux", !"baz"}
196 ; GFX90A: [[META3]] = !{}
197 ;.
198 ; GFX1100: [[META0]] = !{[[META1:![0-9]+]], [[META2:![0-9]+]]}
199 ; GFX1100: [[META1]] = !{!"foo", !"bar"}
200 ; GFX1100: [[META2]] = !{!"bux", !"baz"}
201 ; GFX1100: [[META3]] = !{}
202 ;.