1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt < %s -passes=instsimplify -S | FileCheck %s
4 declare i32 @llvm.smax.i32(i32, i32)
5 declare <2 x i32> @llvm.umin.v2i32(<2 x i32>, <2 x i32>)
7 define i8 @and0(i8 %x) {
15 define <2 x i8> @and0_vec_poison_elt(<2 x i8> %x) {
16 ; CHECK-LABEL: @and0_vec_poison_elt(
17 ; CHECK-NEXT: ret <2 x i8> zeroinitializer
19 %r = and <2 x i8> %x, <i8 poison, i8 0>
23 ; add nsw (xor X, signbit), signbit --> X
25 define <2 x i32> @add_nsw_signbit(<2 x i32> %x) {
26 ; CHECK-LABEL: @add_nsw_signbit(
27 ; CHECK-NEXT: ret <2 x i32> [[X:%.*]]
29 %y = xor <2 x i32> %x, <i32 -2147483648, i32 -2147483648>
30 %z = add nsw <2 x i32> %y, <i32 -2147483648, i32 -2147483648>
34 ; Poison elements in either constant vector are ok.
36 define <2 x i32> @add_nsw_signbit_poison(<2 x i32> %x) {
37 ; CHECK-LABEL: @add_nsw_signbit_poison(
38 ; CHECK-NEXT: ret <2 x i32> [[X:%.*]]
40 %y = xor <2 x i32> %x, <i32 poison, i32 -2147483648>
41 %z = add nsw <2 x i32> %y, <i32 -2147483648, i32 poison>
45 ; add nuw (xor X, signbit), signbit --> X
47 define <2 x i5> @add_nuw_signbit(<2 x i5> %x) {
48 ; CHECK-LABEL: @add_nuw_signbit(
49 ; CHECK-NEXT: ret <2 x i5> [[X:%.*]]
51 %y = xor <2 x i5> %x, <i5 -16, i5 -16>
52 %z = add nuw <2 x i5> %y, <i5 -16, i5 -16>
56 ; Poison elements in either constant vector are ok.
58 define <2 x i5> @add_nuw_signbit_poison(<2 x i5> %x) {
59 ; CHECK-LABEL: @add_nuw_signbit_poison(
60 ; CHECK-NEXT: ret <2 x i5> [[X:%.*]]
62 %y = xor <2 x i5> %x, <i5 -16, i5 poison>
63 %z = add nuw <2 x i5> %y, <i5 poison, i5 -16>
67 define i64 @pow2(i32 %x) {
69 ; CHECK-NEXT: [[NEGX:%.*]] = sub i32 0, [[X:%.*]]
70 ; CHECK-NEXT: [[X2:%.*]] = and i32 [[X]], [[NEGX]]
71 ; CHECK-NEXT: [[E:%.*]] = zext i32 [[X2]] to i64
72 ; CHECK-NEXT: ret i64 [[E]]
75 %x2 = and i32 %x, %negx
76 %e = zext i32 %x2 to i64
78 %e2 = and i64 %e, %nege
82 define i64 @pow2b(i32 %x) {
83 ; CHECK-LABEL: @pow2b(
84 ; CHECK-NEXT: [[SH:%.*]] = shl i32 2, [[X:%.*]]
85 ; CHECK-NEXT: [[E:%.*]] = zext i32 [[SH]] to i64
86 ; CHECK-NEXT: ret i64 [[E]]
89 %e = zext i32 %sh to i64
91 %e2 = and i64 %e, %nege
95 define i32 @pow2b_max(i32 %x, i32 %y) {
96 ; CHECK-LABEL: @pow2b_max(
97 ; CHECK-NEXT: [[SHX:%.*]] = shl i32 2, [[X:%.*]]
98 ; CHECK-NEXT: [[SHY:%.*]] = shl i32 32, [[Y:%.*]]
99 ; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.smax.i32(i32 [[SHX]], i32 [[SHY]])
100 ; CHECK-NEXT: ret i32 [[M]]
103 %shy = shl i32 32, %y
104 %m = call i32 @llvm.smax.i32(i32 %shx, i32 %shy)
106 %r = and i32 %m, %neg
110 ; Power-of-2-or-zero value has no bits in common with its decrement.
112 define i32 @pow2_decrement(i32 %p) {
113 ; CHECK-LABEL: @pow2_decrement(
114 ; CHECK-NEXT: ret i32 0
122 define <2 x i32> @pow2_decrement_commute_vec(<2 x i32> %p) {
123 ; CHECK-LABEL: @pow2_decrement_commute_vec(
124 ; CHECK-NEXT: ret <2 x i32> zeroinitializer
126 %x = and <2 x i32> %p, <i32 2048, i32 2048>
127 %a = add <2 x i32> %x, <i32 -1, i32 -1>
128 %r = and <2 x i32> %x, %a
132 define <2 x i32> @pow2_decrement_min_vec(<2 x i32> %x, <2 x i32> %y) {
133 ; CHECK-LABEL: @pow2_decrement_min_vec(
134 ; CHECK-NEXT: ret <2 x i32> zeroinitializer
136 %p1 = and <2 x i32> %x, <i32 2048, i32 2048>
137 %p2 = shl <2 x i32> <i32 1, i32 1>, %y
138 %m = call <2 x i32> @llvm.umin.v2i32(<2 x i32> %p1, <2 x i32> %p2)
139 %a = add <2 x i32> %m, <i32 -1, i32 -1>
140 %r = and <2 x i32> %m, %a
144 define i1 @and_of_icmps0(i32 %b) {
145 ; CHECK-LABEL: @and_of_icmps0(
146 ; CHECK-NEXT: ret i1 false
149 %2 = icmp ult i32 %1, 4
150 %cmp3 = icmp sgt i32 %b, 2
151 %cmp = and i1 %2, %cmp3
155 define <2 x i1> @and_of_icmps0_vec(<2 x i32> %b) {
156 ; CHECK-LABEL: @and_of_icmps0_vec(
157 ; CHECK-NEXT: ret <2 x i1> zeroinitializer
159 %1 = add <2 x i32> %b, <i32 2, i32 2>
160 %2 = icmp ult <2 x i32> %1, <i32 4, i32 4>
161 %cmp3 = icmp sgt <2 x i32> %b, <i32 2, i32 2>
162 %cmp = and <2 x i1> %2, %cmp3
166 define i1 @and_of_icmps1(i32 %b) {
167 ; CHECK-LABEL: @and_of_icmps1(
168 ; CHECK-NEXT: ret i1 false
170 %1 = add nsw i32 %b, 2
171 %2 = icmp slt i32 %1, 4
172 %cmp3 = icmp sgt i32 %b, 2
173 %cmp = and i1 %2, %cmp3
177 define <2 x i1> @and_of_icmps1_vec(<2 x i32> %b) {
178 ; CHECK-LABEL: @and_of_icmps1_vec(
179 ; CHECK-NEXT: ret <2 x i1> zeroinitializer
181 %1 = add nsw <2 x i32> %b, <i32 2, i32 2>
182 %2 = icmp slt <2 x i32> %1, <i32 4, i32 4>
183 %cmp3 = icmp sgt <2 x i32> %b, <i32 2, i32 2>
184 %cmp = and <2 x i1> %2, %cmp3
188 define i1 @and_of_icmps2(i32 %b) {
189 ; CHECK-LABEL: @and_of_icmps2(
190 ; CHECK-NEXT: ret i1 false
193 %2 = icmp ule i32 %1, 3
194 %cmp3 = icmp sgt i32 %b, 2
195 %cmp = and i1 %2, %cmp3
199 define <2 x i1> @and_of_icmps2_vec(<2 x i32> %b) {
200 ; CHECK-LABEL: @and_of_icmps2_vec(
201 ; CHECK-NEXT: ret <2 x i1> zeroinitializer
203 %1 = add <2 x i32> %b, <i32 2, i32 2>
204 %2 = icmp ule <2 x i32> %1, <i32 3, i32 3>
205 %cmp3 = icmp sgt <2 x i32> %b, <i32 2, i32 2>
206 %cmp = and <2 x i1> %2, %cmp3
210 define i1 @and_of_icmps3(i32 %b) {
211 ; CHECK-LABEL: @and_of_icmps3(
212 ; CHECK-NEXT: ret i1 false
214 %1 = add nsw i32 %b, 2
215 %2 = icmp sle i32 %1, 3
216 %cmp3 = icmp sgt i32 %b, 2
217 %cmp = and i1 %2, %cmp3
221 define <2 x i1> @and_of_icmps3_vec(<2 x i32> %b) {
222 ; CHECK-LABEL: @and_of_icmps3_vec(
223 ; CHECK-NEXT: ret <2 x i1> zeroinitializer
225 %1 = add nsw <2 x i32> %b, <i32 2, i32 2>
226 %2 = icmp sle <2 x i32> %1, <i32 3, i32 3>
227 %cmp3 = icmp sgt <2 x i32> %b, <i32 2, i32 2>
228 %cmp = and <2 x i1> %2, %cmp3
232 define i1 @and_of_icmps4(i32 %b) {
233 ; CHECK-LABEL: @and_of_icmps4(
234 ; CHECK-NEXT: ret i1 false
236 %1 = add nuw i32 %b, 2
237 %2 = icmp ult i32 %1, 4
238 %cmp3 = icmp ugt i32 %b, 2
239 %cmp = and i1 %2, %cmp3
243 define <2 x i1> @and_of_icmps4_vec(<2 x i32> %b) {
244 ; CHECK-LABEL: @and_of_icmps4_vec(
245 ; CHECK-NEXT: ret <2 x i1> zeroinitializer
247 %1 = add nuw <2 x i32> %b, <i32 2, i32 2>
248 %2 = icmp ult <2 x i32> %1, <i32 4, i32 4>
249 %cmp3 = icmp ugt <2 x i32> %b, <i32 2, i32 2>
250 %cmp = and <2 x i1> %2, %cmp3
254 define i1 @and_of_icmps5(i32 %b) {
255 ; CHECK-LABEL: @and_of_icmps5(
256 ; CHECK-NEXT: ret i1 false
258 %1 = add nuw i32 %b, 2
259 %2 = icmp ule i32 %1, 3
260 %cmp3 = icmp ugt i32 %b, 2
261 %cmp = and i1 %2, %cmp3
265 define <2 x i1> @and_of_icmps5_vec(<2 x i32> %b) {
266 ; CHECK-LABEL: @and_of_icmps5_vec(
267 ; CHECK-NEXT: ret <2 x i1> zeroinitializer
269 %1 = add nuw <2 x i32> %b, <i32 2, i32 2>
270 %2 = icmp ule <2 x i32> %1, <i32 3, i32 3>
271 %cmp3 = icmp ugt <2 x i32> %b, <i32 2, i32 2>
272 %cmp = and <2 x i1> %2, %cmp3
276 define i1 @or_of_icmps0(i32 %b) {
277 ; CHECK-LABEL: @or_of_icmps0(
278 ; CHECK-NEXT: ret i1 true
281 %2 = icmp uge i32 %1, 4
282 %cmp3 = icmp sle i32 %b, 2
283 %cmp = or i1 %2, %cmp3
287 define <2 x i1> @or_of_icmps0_vec(<2 x i32> %b) {
288 ; CHECK-LABEL: @or_of_icmps0_vec(
289 ; CHECK-NEXT: ret <2 x i1> splat (i1 true)
291 %1 = add <2 x i32> %b, <i32 2, i32 2>
292 %2 = icmp uge <2 x i32> %1, <i32 4, i32 4>
293 %cmp3 = icmp sle <2 x i32> %b, <i32 2, i32 2>
294 %cmp = or <2 x i1> %2, %cmp3
298 define i1 @or_of_icmps1(i32 %b) {
299 ; CHECK-LABEL: @or_of_icmps1(
300 ; CHECK-NEXT: ret i1 true
302 %1 = add nsw i32 %b, 2
303 %2 = icmp sge i32 %1, 4
304 %cmp3 = icmp sle i32 %b, 2
305 %cmp = or i1 %2, %cmp3
309 define <2 x i1> @or_of_icmps1_vec(<2 x i32> %b) {
310 ; CHECK-LABEL: @or_of_icmps1_vec(
311 ; CHECK-NEXT: ret <2 x i1> splat (i1 true)
313 %1 = add nsw <2 x i32> %b, <i32 2, i32 2>
314 %2 = icmp sge <2 x i32> %1, <i32 4, i32 4>
315 %cmp3 = icmp sle <2 x i32> %b, <i32 2, i32 2>
316 %cmp = or <2 x i1> %2, %cmp3
320 define i1 @or_of_icmps2(i32 %b) {
321 ; CHECK-LABEL: @or_of_icmps2(
322 ; CHECK-NEXT: ret i1 true
325 %2 = icmp ugt i32 %1, 3
326 %cmp3 = icmp sle i32 %b, 2
327 %cmp = or i1 %2, %cmp3
331 define <2 x i1> @or_of_icmps2_vec(<2 x i32> %b) {
332 ; CHECK-LABEL: @or_of_icmps2_vec(
333 ; CHECK-NEXT: ret <2 x i1> splat (i1 true)
335 %1 = add <2 x i32> %b, <i32 2, i32 2>
336 %2 = icmp ugt <2 x i32> %1, <i32 3, i32 3>
337 %cmp3 = icmp sle <2 x i32> %b, <i32 2, i32 2>
338 %cmp = or <2 x i1> %2, %cmp3
342 define i1 @or_of_icmps3(i32 %b) {
343 ; CHECK-LABEL: @or_of_icmps3(
344 ; CHECK-NEXT: ret i1 true
346 %1 = add nsw i32 %b, 2
347 %2 = icmp sgt i32 %1, 3
348 %cmp3 = icmp sle i32 %b, 2
349 %cmp = or i1 %2, %cmp3
353 define <2 x i1> @or_of_icmps3_vec(<2 x i32> %b) {
354 ; CHECK-LABEL: @or_of_icmps3_vec(
355 ; CHECK-NEXT: ret <2 x i1> splat (i1 true)
357 %1 = add nsw <2 x i32> %b, <i32 2, i32 2>
358 %2 = icmp sgt <2 x i32> %1, <i32 3, i32 3>
359 %cmp3 = icmp sle <2 x i32> %b, <i32 2, i32 2>
360 %cmp = or <2 x i1> %2, %cmp3
364 define i1 @or_of_icmps4(i32 %b) {
365 ; CHECK-LABEL: @or_of_icmps4(
366 ; CHECK-NEXT: ret i1 true
368 %1 = add nuw i32 %b, 2
369 %2 = icmp uge i32 %1, 4
370 %cmp3 = icmp ule i32 %b, 2
371 %cmp = or i1 %2, %cmp3
375 define <2 x i1> @or_of_icmps4_vec(<2 x i32> %b) {
376 ; CHECK-LABEL: @or_of_icmps4_vec(
377 ; CHECK-NEXT: ret <2 x i1> splat (i1 true)
379 %1 = add nuw <2 x i32> %b, <i32 2, i32 2>
380 %2 = icmp uge <2 x i32> %1, <i32 4, i32 4>
381 %cmp3 = icmp ule <2 x i32> %b, <i32 2, i32 2>
382 %cmp = or <2 x i1> %2, %cmp3
386 define i1 @or_of_icmps5(i32 %b) {
387 ; CHECK-LABEL: @or_of_icmps5(
388 ; CHECK-NEXT: ret i1 true
390 %1 = add nuw i32 %b, 2
391 %2 = icmp ugt i32 %1, 3
392 %cmp3 = icmp ule i32 %b, 2
393 %cmp = or i1 %2, %cmp3
397 define <2 x i1> @or_of_icmps5_vec(<2 x i32> %b) {
398 ; CHECK-LABEL: @or_of_icmps5_vec(
399 ; CHECK-NEXT: ret <2 x i1> splat (i1 true)
401 %1 = add nuw <2 x i32> %b, <i32 2, i32 2>
402 %2 = icmp ugt <2 x i32> %1, <i32 3, i32 3>
403 %cmp3 = icmp ule <2 x i32> %b, <i32 2, i32 2>
404 %cmp = or <2 x i1> %2, %cmp3
408 define i32 @neg_nuw(i32 %x) {
409 ; CHECK-LABEL: @neg_nuw(
410 ; CHECK-NEXT: ret i32 0
412 %neg = sub nuw i32 0, %x
416 ; PR27869 - Look through casts to eliminate cmps and bitwise logic.
418 define i32 @and_of_zexted_icmps(i32 %i) {
419 ; CHECK-LABEL: @and_of_zexted_icmps(
420 ; CHECK-NEXT: ret i32 0
422 %cmp0 = icmp eq i32 %i, 0
423 %conv0 = zext i1 %cmp0 to i32
424 %cmp1 = icmp ugt i32 %i, 4
425 %conv1 = zext i1 %cmp1 to i32
426 %and = and i32 %conv0, %conv1
430 ; Make sure vectors work too.
432 define <4 x i32> @and_of_zexted_icmps_vec(<4 x i32> %i) {
433 ; CHECK-LABEL: @and_of_zexted_icmps_vec(
434 ; CHECK-NEXT: ret <4 x i32> zeroinitializer
436 %cmp0 = icmp eq <4 x i32> %i, zeroinitializer
437 %conv0 = zext <4 x i1> %cmp0 to <4 x i32>
438 %cmp1 = icmp slt <4 x i32> %i, zeroinitializer
439 %conv1 = zext <4 x i1> %cmp1 to <4 x i32>
440 %and = and <4 x i32> %conv0, %conv1
444 ; Try a different cast and weird types.
446 define i5 @and_of_sexted_icmps(i3 %i) {
447 ; CHECK-LABEL: @and_of_sexted_icmps(
448 ; CHECK-NEXT: ret i5 0
450 %cmp0 = icmp eq i3 %i, 0
451 %conv0 = sext i1 %cmp0 to i5
452 %cmp1 = icmp ugt i3 %i, 1
453 %conv1 = sext i1 %cmp1 to i5
454 %and = and i5 %conv0, %conv1
458 ; Try a different cast and weird vector types.
460 define i3 @and_of_bitcast_icmps_vec(<3 x i65> %i) {
461 ; CHECK-LABEL: @and_of_bitcast_icmps_vec(
462 ; CHECK-NEXT: ret i3 0
464 %cmp0 = icmp sgt <3 x i65> %i, zeroinitializer
465 %conv0 = bitcast <3 x i1> %cmp0 to i3
466 %cmp1 = icmp slt <3 x i65> %i, zeroinitializer
467 %conv1 = bitcast <3 x i1> %cmp1 to i3
468 %and = and i3 %conv0, %conv1
472 ; We can't do this if the casts are different.
474 define i16 @and_of_different_cast_icmps(i8 %i) {
475 ; CHECK-LABEL: @and_of_different_cast_icmps(
476 ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i8 [[I:%.*]], 0
477 ; CHECK-NEXT: [[CONV0:%.*]] = zext i1 [[CMP0]] to i16
478 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[I]], 1
479 ; CHECK-NEXT: [[CONV1:%.*]] = sext i1 [[CMP1]] to i16
480 ; CHECK-NEXT: [[AND:%.*]] = and i16 [[CONV0]], [[CONV1]]
481 ; CHECK-NEXT: ret i16 [[AND]]
483 %cmp0 = icmp eq i8 %i, 0
484 %conv0 = zext i1 %cmp0 to i16
485 %cmp1 = icmp eq i8 %i, 1
486 %conv1 = sext i1 %cmp1 to i16
487 %and = and i16 %conv0, %conv1
491 define <2 x i3> @and_of_different_cast_icmps_vec(<2 x i8> %i, <2 x i16> %j) {
492 ; CHECK-LABEL: @and_of_different_cast_icmps_vec(
493 ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq <2 x i8> [[I:%.*]], zeroinitializer
494 ; CHECK-NEXT: [[CONV0:%.*]] = zext <2 x i1> [[CMP0]] to <2 x i3>
495 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i16> [[J:%.*]], splat (i16 1)
496 ; CHECK-NEXT: [[CONV1:%.*]] = zext <2 x i1> [[CMP1]] to <2 x i3>
497 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i3> [[CONV0]], [[CONV1]]
498 ; CHECK-NEXT: ret <2 x i3> [[AND]]
500 %cmp0 = icmp eq <2 x i8> %i, zeroinitializer
501 %conv0 = zext <2 x i1> %cmp0 to <2 x i3>
502 %cmp1 = icmp ugt <2 x i16> %j, <i16 1, i16 1>
503 %conv1 = zext <2 x i1> %cmp1 to <2 x i3>
504 %and = and <2 x i3> %conv0, %conv1
510 define i32 @or_of_zexted_icmps(i32 %i) {
511 ; CHECK-LABEL: @or_of_zexted_icmps(
512 ; CHECK-NEXT: ret i32 1
514 %cmp0 = icmp ne i32 %i, 0
515 %conv0 = zext i1 %cmp0 to i32
516 %cmp1 = icmp uge i32 4, %i
517 %conv1 = zext i1 %cmp1 to i32
518 %or = or i32 %conv0, %conv1
522 ; Try a different cast and weird vector types.
524 define i3 @or_of_bitcast_icmps_vec(<3 x i65> %i) {
525 ; CHECK-LABEL: @or_of_bitcast_icmps_vec(
526 ; CHECK-NEXT: ret i3 -1
528 %cmp0 = icmp sge <3 x i65> %i, zeroinitializer
529 %conv0 = bitcast <3 x i1> %cmp0 to i3
530 %cmp1 = icmp slt <3 x i65> %i, zeroinitializer
531 %conv1 = bitcast <3 x i1> %cmp1 to i3
532 %or = or i3 %conv0, %conv1
536 ; We can't simplify if the casts are different.
538 define i16 @or_of_different_cast_icmps(i8 %i) {
539 ; CHECK-LABEL: @or_of_different_cast_icmps(
540 ; CHECK-NEXT: [[CMP0:%.*]] = icmp ne i8 [[I:%.*]], 0
541 ; CHECK-NEXT: [[CONV0:%.*]] = zext i1 [[CMP0]] to i16
542 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i8 [[I]], 1
543 ; CHECK-NEXT: [[CONV1:%.*]] = sext i1 [[CMP1]] to i16
544 ; CHECK-NEXT: [[OR:%.*]] = or i16 [[CONV0]], [[CONV1]]
545 ; CHECK-NEXT: ret i16 [[OR]]
547 %cmp0 = icmp ne i8 %i, 0
548 %conv0 = zext i1 %cmp0 to i16
549 %cmp1 = icmp ne i8 %i, 1
550 %conv1 = sext i1 %cmp1 to i16
551 %or = or i16 %conv0, %conv1
555 ; (A & ~B) | (A ^ B) -> A ^ B
557 define i3 @or_xor_andn_commute0(i3 %a, i3 %b) {
558 ; CHECK-LABEL: @or_xor_andn_commute0(
559 ; CHECK-NEXT: [[XOR:%.*]] = xor i3 [[A:%.*]], [[B:%.*]]
560 ; CHECK-NEXT: ret i3 [[XOR]]
563 %and = and i3 %a, %neg
565 %or = or i3 %and, %xor
569 define i32 @or_xor_andn_commute1(i32 %a, i32 %b) {
570 ; CHECK-LABEL: @or_xor_andn_commute1(
571 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
572 ; CHECK-NEXT: ret i32 [[XOR]]
574 %neg = xor i32 %b, -1
575 %and = and i32 %neg, %a
576 %xor = xor i32 %a, %b
577 %or = or i32 %and, %xor
581 define <2 x i32> @or_xor_andn_commute2(<2 x i32> %a, <2 x i32> %b) {
582 ; CHECK-LABEL: @or_xor_andn_commute2(
583 ; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i32> [[A:%.*]], [[B:%.*]]
584 ; CHECK-NEXT: ret <2 x i32> [[XOR]]
586 %xor = xor <2 x i32> %a, %b
587 %neg = xor <2 x i32> %b, <i32 -1, i32 poison>
588 %and = and <2 x i32> %a, %neg
589 %or = or <2 x i32> %xor, %and
593 define i32 @or_xor_andn_commute3(i32 %a, i32 %b) {
594 ; CHECK-LABEL: @or_xor_andn_commute3(
595 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
596 ; CHECK-NEXT: ret i32 [[XOR]]
598 %xor = xor i32 %a, %b
599 %neg = xor i32 %b, -1
600 %and = and i32 %neg, %a
601 %or = or i32 %xor, %and
605 define i32 @or_xor_andn_commute4(i32 %a, i32 %b) {
606 ; CHECK-LABEL: @or_xor_andn_commute4(
607 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[B:%.*]], [[A:%.*]]
608 ; CHECK-NEXT: ret i32 [[XOR]]
610 %neg = xor i32 %b, -1
611 %and = and i32 %a, %neg
612 %xor = xor i32 %b, %a
613 %or = or i32 %and, %xor
617 define i32 @or_xor_andn_commute5(i32 %a, i32 %b) {
618 ; CHECK-LABEL: @or_xor_andn_commute5(
619 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[B:%.*]], [[A:%.*]]
620 ; CHECK-NEXT: ret i32 [[XOR]]
622 %neg = xor i32 %b, -1
623 %and = and i32 %neg, %a
624 %xor = xor i32 %b, %a
625 %or = or i32 %and, %xor
629 define i32 @or_xor_andn_commute6(i32 %a, i32 %b) {
630 ; CHECK-LABEL: @or_xor_andn_commute6(
631 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[B:%.*]], [[A:%.*]]
632 ; CHECK-NEXT: ret i32 [[XOR]]
634 %xor = xor i32 %b, %a
635 %neg = xor i32 %b, -1
636 %and = and i32 %a, %neg
637 %or = or i32 %xor, %and
641 define i32 @or_xor_andn_commute7(i32 %a, i32 %b) {
642 ; CHECK-LABEL: @or_xor_andn_commute7(
643 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[B:%.*]], [[A:%.*]]
644 ; CHECK-NEXT: ret i32 [[XOR]]
646 %xor = xor i32 %b, %a
647 %neg = xor i32 %b, -1
648 %and = and i32 %neg, %a
649 %or = or i32 %xor, %and
653 ; (~A ^ B) | (A & B) -> ~A ^ B
655 define i32 @or_xorn_and_commute0(i32 %a, i32 %b) {
656 ; CHECK-LABEL: @or_xorn_and_commute0(
657 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
658 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[NEGA]], [[B:%.*]]
659 ; CHECK-NEXT: ret i32 [[XOR]]
661 %nega = xor i32 %a, -1
662 %and = and i32 %a, %b
663 %xor = xor i32 %nega, %b
664 %or = or i32 %xor, %and
668 define i3 @or_xorn_and_commute1(i3 %a, i3 %b) {
669 ; CHECK-LABEL: @or_xorn_and_commute1(
670 ; CHECK-NEXT: [[NEGA:%.*]] = xor i3 [[A:%.*]], -1
671 ; CHECK-NEXT: [[XOR:%.*]] = xor i3 [[B:%.*]], [[NEGA]]
672 ; CHECK-NEXT: ret i3 [[XOR]]
674 %nega = xor i3 %a, -1
676 %xor = xor i3 %b, %nega
677 %or = or i3 %xor, %and
681 define <2 x i32> @or_xorn_and_commute2(<2 x i32> %a, <2 x i32> %b) {
682 ; CHECK-LABEL: @or_xorn_and_commute2(
683 ; CHECK-NEXT: [[NEGA:%.*]] = xor <2 x i32> [[A:%.*]], splat (i32 -1)
684 ; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i32> [[B:%.*]], [[NEGA]]
685 ; CHECK-NEXT: ret <2 x i32> [[XOR]]
687 %nega = xor <2 x i32> %a, <i32 -1, i32 -1>
688 %and = and <2 x i32> %b, %a
689 %xor = xor <2 x i32> %b, %nega
690 %or = or <2 x i32> %xor, %and
694 ; This is not safe to fold because the extra logic ops limit the undef-ness of the result.
696 define <2 x i32> @or_xorn_and_commute2_undef(<2 x i32> %a, <2 x i32> %b) {
697 ; CHECK-LABEL: @or_xorn_and_commute2_undef(
698 ; CHECK-NEXT: [[NEGA:%.*]] = xor <2 x i32> [[A:%.*]], <i32 undef, i32 -1>
699 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[B:%.*]], [[A]]
700 ; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i32> [[B]], [[NEGA]]
701 ; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[XOR]], [[AND]]
702 ; CHECK-NEXT: ret <2 x i32> [[OR]]
704 %nega = xor <2 x i32> %a, <i32 undef, i32 -1>
705 %and = and <2 x i32> %b, %a
706 %xor = xor <2 x i32> %b, %nega
707 %or = or <2 x i32> %xor, %and
711 ; Unlike the above test, this is safe to fold.
713 define <2 x i32> @or_xorn_and_commute2_poison(<2 x i32> %a, <2 x i32> %b) {
714 ; CHECK-LABEL: @or_xorn_and_commute2_poison(
715 ; CHECK-NEXT: [[NEGA:%.*]] = xor <2 x i32> [[A:%.*]], <i32 poison, i32 -1>
716 ; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i32> [[B:%.*]], [[NEGA]]
717 ; CHECK-NEXT: ret <2 x i32> [[XOR]]
719 %nega = xor <2 x i32> %a, <i32 poison, i32 -1>
720 %and = and <2 x i32> %b, %a
721 %xor = xor <2 x i32> %b, %nega
722 %or = or <2 x i32> %xor, %and
726 define i32 @or_xorn_and_commute3(i32 %a, i32 %b) {
727 ; CHECK-LABEL: @or_xorn_and_commute3(
728 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
729 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[NEGA]], [[B:%.*]]
730 ; CHECK-NEXT: ret i32 [[XOR]]
732 %nega = xor i32 %a, -1
733 %and = and i32 %b, %a
734 %xor = xor i32 %nega, %b
735 %or = or i32 %xor, %and
739 define i32 @or_xorn_and_commute4(i32 %a, i32 %b) {
740 ; CHECK-LABEL: @or_xorn_and_commute4(
741 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
742 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[NEGA]], [[B:%.*]]
743 ; CHECK-NEXT: ret i32 [[XOR]]
745 %nega = xor i32 %a, -1
746 %and = and i32 %a, %b
747 %xor = xor i32 %nega, %b
748 %or = or i32 %and, %xor
752 define i32 @or_xorn_and_commute5(i32 %a, i32 %b) {
753 ; CHECK-LABEL: @or_xorn_and_commute5(
754 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
755 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[B:%.*]], [[NEGA]]
756 ; CHECK-NEXT: ret i32 [[XOR]]
758 %nega = xor i32 %a, -1
759 %and = and i32 %a, %b
760 %xor = xor i32 %b, %nega
761 %or = or i32 %and, %xor
765 define i32 @or_xorn_and_commute6(i32 %a, i32 %b) {
766 ; CHECK-LABEL: @or_xorn_and_commute6(
767 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
768 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[B:%.*]], [[NEGA]]
769 ; CHECK-NEXT: ret i32 [[XOR]]
771 %nega = xor i32 %a, -1
772 %and = and i32 %b, %a
773 %xor = xor i32 %b, %nega
774 %or = or i32 %and, %xor
778 define i32 @or_xorn_and_commute7(i32 %a, i32 %b) {
779 ; CHECK-LABEL: @or_xorn_and_commute7(
780 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
781 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[NEGA]], [[B:%.*]]
782 ; CHECK-NEXT: ret i32 [[XOR]]
784 %nega = xor i32 %a, -1
785 %and = and i32 %b, %a
786 %xor = xor i32 %nega, %b
787 %or = or i32 %and, %xor
791 define i8 @lshr_perfect_mask(i8 %x) {
792 ; CHECK-LABEL: @lshr_perfect_mask(
793 ; CHECK-NEXT: [[SH:%.*]] = lshr i8 [[X:%.*]], 5
794 ; CHECK-NEXT: ret i8 [[SH]]
797 %mask = and i8 %sh, 7 ; 0x07
801 define <2 x i8> @lshr_oversized_mask_splat(<2 x i8> %x) {
802 ; CHECK-LABEL: @lshr_oversized_mask_splat(
803 ; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i8> [[X:%.*]], splat (i8 5)
804 ; CHECK-NEXT: ret <2 x i8> [[SH]]
806 %sh = lshr <2 x i8> %x, <i8 5, i8 5>
807 %mask = and <2 x i8> %sh, <i8 135, i8 135> ; 0x87
811 define i8 @lshr_undersized_mask(i8 %x) {
812 ; CHECK-LABEL: @lshr_undersized_mask(
813 ; CHECK-NEXT: [[SH:%.*]] = lshr i8 [[X:%.*]], 5
814 ; CHECK-NEXT: [[MASK:%.*]] = and i8 [[SH]], -2
815 ; CHECK-NEXT: ret i8 [[MASK]]
818 %mask = and i8 %sh, -2 ; 0xFE
822 define <2 x i8> @shl_perfect_mask_splat(<2 x i8> %x) {
823 ; CHECK-LABEL: @shl_perfect_mask_splat(
824 ; CHECK-NEXT: [[SH:%.*]] = shl <2 x i8> [[X:%.*]], splat (i8 6)
825 ; CHECK-NEXT: ret <2 x i8> [[SH]]
827 %sh = shl <2 x i8> %x, <i8 6, i8 6>
828 %mask = and <2 x i8> %sh, <i8 192, i8 192> ; 0xC0
832 define i8 @shl_oversized_mask(i8 %x) {
833 ; CHECK-LABEL: @shl_oversized_mask(
834 ; CHECK-NEXT: [[SH:%.*]] = shl i8 [[X:%.*]], 6
835 ; CHECK-NEXT: ret i8 [[SH]]
838 %mask = and i8 %sh, 195 ; 0xC3
842 define <2 x i8> @shl_undersized_mask_splat(<2 x i8> %x) {
843 ; CHECK-LABEL: @shl_undersized_mask_splat(
844 ; CHECK-NEXT: [[SH:%.*]] = shl <2 x i8> [[X:%.*]], splat (i8 6)
845 ; CHECK-NEXT: [[MASK:%.*]] = and <2 x i8> [[SH]], splat (i8 -120)
846 ; CHECK-NEXT: ret <2 x i8> [[MASK]]
848 %sh = shl <2 x i8> %x, <i8 6, i8 6>
849 %mask = and <2 x i8> %sh, <i8 136, i8 136> ; 0x88
853 define i32 @reversed_not(i32 %a) {
854 ; CHECK-LABEL: @reversed_not(
855 ; CHECK-NEXT: ret i32 -1
857 %nega = xor i32 -1, %a
858 %or = or i32 %a, %nega
862 define i64 @shl_or_and1(i32 %a, i1 %b) {
863 ; CHECK-LABEL: @shl_or_and1(
864 ; CHECK-NEXT: [[T2:%.*]] = zext i1 [[B:%.*]] to i64
865 ; CHECK-NEXT: ret i64 [[T2]]
867 %t1 = zext i32 %a to i64
868 %t2 = zext i1 %b to i64
869 %t3 = shl nuw i64 %t1, 32
870 %t4 = or i64 %t2, %t3
875 define i64 @shl_or_and2(i32 %a, i1 %b) {
876 ; CHECK-LABEL: @shl_or_and2(
877 ; CHECK-NEXT: [[T1:%.*]] = zext i1 [[B:%.*]] to i64
878 ; CHECK-NEXT: [[T3:%.*]] = shl nuw i64 [[T1]], 32
879 ; CHECK-NEXT: ret i64 [[T3]]
881 %t1 = zext i1 %b to i64
882 %t2 = zext i32 %a to i64
883 %t3 = shl nuw i64 %t1, 32
884 %t4 = or i64 %t2, %t3
885 %t5 = and i64 %t4, 4294967296
889 ; concatenate two 32-bit integers and extract lower 32-bit
890 define i64 @shl_or_and3(i32 %a, i32 %b) {
891 ; CHECK-LABEL: @shl_or_and3(
892 ; CHECK-NEXT: [[T2:%.*]] = zext i32 [[B:%.*]] to i64
893 ; CHECK-NEXT: ret i64 [[T2]]
895 %t1 = zext i32 %a to i64
896 %t2 = zext i32 %b to i64
897 %t3 = shl nuw i64 %t1, 32
898 %t4 = or i64 %t2, %t3
899 %t5 = and i64 %t4, 4294967295
903 ; concatenate two 16-bit integers and extract higher 16-bit
904 define i32 @shl_or_and4(i16 %a, i16 %b) {
905 ; CHECK-LABEL: @shl_or_and4(
906 ; CHECK-NEXT: [[T1:%.*]] = zext i16 [[A:%.*]] to i32
907 ; CHECK-NEXT: [[T3:%.*]] = shl nuw i32 [[T1]], 16
908 ; CHECK-NEXT: ret i32 [[T3]]
910 %t1 = zext i16 %a to i32
911 %t2 = zext i16 %b to i32
912 %t3 = shl nuw i32 %t1, 16
913 %t4 = or i32 %t2, %t3
914 %t5 = and i32 %t4, 4294901760 ; mask with 0xFFFF0000
918 define i128 @shl_or_and5(i64 %a, i1 %b) {
919 ; CHECK-LABEL: @shl_or_and5(
920 ; CHECK-NEXT: [[T2:%.*]] = zext i1 [[B:%.*]] to i128
921 ; CHECK-NEXT: ret i128 [[T2]]
923 %t1 = zext i64 %a to i128
924 %t2 = zext i1 %b to i128
925 %t3 = shl nuw i128 %t1, 64
926 %t4 = or i128 %t2, %t3
927 %t5 = and i128 %t4, 1
931 ; A variation of above test cases; it fails due to the mask value
932 define i32 @shl_or_and6(i16 %a, i16 %b) {
933 ; CHECK-LABEL: @shl_or_and6(
934 ; CHECK-NEXT: [[T1:%.*]] = zext i16 [[A:%.*]] to i32
935 ; CHECK-NEXT: [[T2:%.*]] = zext i16 [[B:%.*]] to i32
936 ; CHECK-NEXT: [[T3:%.*]] = shl nuw i32 [[T1]], 16
937 ; CHECK-NEXT: [[T4:%.*]] = or i32 [[T2]], [[T3]]
938 ; CHECK-NEXT: [[T5:%.*]] = and i32 [[T4]], -65535
939 ; CHECK-NEXT: ret i32 [[T5]]
941 %t1 = zext i16 %a to i32
942 %t2 = zext i16 %b to i32
943 %t3 = shl nuw i32 %t1, 16
944 %t4 = or i32 %t2, %t3
945 %t5 = and i32 %t4, 4294901761 ; mask with 0xFFFF0001
949 ; A variation of above test cases; it fails due to the mask value
950 define i32 @shl_or_and7(i16 %a, i16 %b) {
951 ; CHECK-LABEL: @shl_or_and7(
952 ; CHECK-NEXT: [[T1:%.*]] = zext i16 [[A:%.*]] to i32
953 ; CHECK-NEXT: [[T2:%.*]] = zext i16 [[B:%.*]] to i32
954 ; CHECK-NEXT: [[T3:%.*]] = shl nuw i32 [[T1]], 16
955 ; CHECK-NEXT: [[T4:%.*]] = or i32 [[T2]], [[T3]]
956 ; CHECK-NEXT: [[T5:%.*]] = and i32 [[T4]], -131072
957 ; CHECK-NEXT: ret i32 [[T5]]
959 %t1 = zext i16 %a to i32
960 %t2 = zext i16 %b to i32
961 %t3 = shl nuw i32 %t1, 16
962 %t4 = or i32 %t2, %t3
963 %t5 = and i32 %t4, 4294836224 ; mask with 0xFFFE0000
967 ; A variation of above test cases; it fails due to the mask value
968 define i32 @shl_or_and8(i16 %a, i16 %b) {
969 ; CHECK-LABEL: @shl_or_and8(
970 ; CHECK-NEXT: [[T1:%.*]] = zext i16 [[A:%.*]] to i32
971 ; CHECK-NEXT: [[T2:%.*]] = zext i16 [[B:%.*]] to i32
972 ; CHECK-NEXT: [[T3:%.*]] = shl nuw i32 [[T1]], 16
973 ; CHECK-NEXT: [[T4:%.*]] = or i32 [[T2]], [[T3]]
974 ; CHECK-NEXT: [[T5:%.*]] = and i32 [[T4]], 131071
975 ; CHECK-NEXT: ret i32 [[T5]]
977 %t1 = zext i16 %a to i32
978 %t2 = zext i16 %b to i32
979 %t3 = shl nuw i32 %t1, 16
980 %t4 = or i32 %t2, %t3
981 %t5 = and i32 %t4, 131071 ; mask with 0x1FFFF
985 define <2 x i64> @shl_or_and1v(<2 x i32> %a, <2 x i1> %b) {
986 ; CHECK-LABEL: @shl_or_and1v(
987 ; CHECK-NEXT: [[T2:%.*]] = zext <2 x i1> [[B:%.*]] to <2 x i64>
988 ; CHECK-NEXT: ret <2 x i64> [[T2]]
990 %t1 = zext <2 x i32> %a to <2 x i64>
991 %t2 = zext <2 x i1> %b to <2 x i64>
992 %t3 = shl nuw <2 x i64> %t1, <i64 32, i64 32>
993 %t4 = or <2 x i64> %t3, %t2
994 %t5 = and <2 x i64> %t4, <i64 1, i64 1>
998 define <2 x i64> @shl_or_and2v(<2 x i32> %a, <2 x i1> %b) {
999 ; CHECK-LABEL: @shl_or_and2v(
1000 ; CHECK-NEXT: [[T1:%.*]] = zext <2 x i1> [[B:%.*]] to <2 x i64>
1001 ; CHECK-NEXT: [[T3:%.*]] = shl nuw <2 x i64> [[T1]], splat (i64 32)
1002 ; CHECK-NEXT: ret <2 x i64> [[T3]]
1004 %t1 = zext <2 x i1> %b to <2 x i64>
1005 %t2 = zext <2 x i32> %a to <2 x i64>
1006 %t3 = shl nuw <2 x i64> %t1, <i64 32, i64 32>
1007 %t4 = or <2 x i64> %t2, %t3
1008 %t5 = and <2 x i64> %t4, <i64 4294967296, i64 4294967296>
1012 ; A variation of above test case, but fails due to the mask value
1013 define <2 x i32> @shl_or_and3v(<2 x i16> %a, <2 x i16> %b) {
1014 ; CHECK-LABEL: @shl_or_and3v(
1015 ; CHECK-NEXT: [[T1:%.*]] = zext <2 x i16> [[A:%.*]] to <2 x i32>
1016 ; CHECK-NEXT: [[T2:%.*]] = zext <2 x i16> [[B:%.*]] to <2 x i32>
1017 ; CHECK-NEXT: [[T3:%.*]] = shl nuw <2 x i32> [[T1]], splat (i32 16)
1018 ; CHECK-NEXT: [[T4:%.*]] = or <2 x i32> [[T2]], [[T3]]
1019 ; CHECK-NEXT: [[T5:%.*]] = and <2 x i32> [[T4]], splat (i32 -65535)
1020 ; CHECK-NEXT: ret <2 x i32> [[T5]]
1022 %t1 = zext <2 x i16> %a to <2 x i32>
1023 %t2 = zext <2 x i16> %b to <2 x i32>
1024 %t3 = shl nuw <2 x i32> %t1, <i32 16, i32 16>
1025 %t4 = or <2 x i32> %t2, %t3
1026 %t5 = and <2 x i32> %t4, <i32 4294901761, i32 4294901761> ; mask with 0xFFFF0001
1030 define i8 @and_add_sub(i8 %x) {
1031 ; CHECK-LABEL: @and_add_sub(
1032 ; CHECK-NEXT: ret i8 0
1040 define <2 x i8> @and_sub_add(<2 x i8> %x) {
1041 ; CHECK-LABEL: @and_sub_add(
1042 ; CHECK-NEXT: ret <2 x i8> zeroinitializer
1044 %a = add <2 x i8> %x, <i8 -4, i8 -4>
1045 %s = sub <2 x i8> <i8 3, i8 3>, %x
1046 %r = and <2 x i8> %s, %a
1050 define i89 @or_add_sub(i89 %x) {
1051 ; CHECK-LABEL: @or_add_sub(
1052 ; CHECK-NEXT: ret i89 -1
1060 define <3 x i8> @or_sub_add(<3 x i8> %x) {
1061 ; CHECK-LABEL: @or_sub_add(
1062 ; CHECK-NEXT: ret <3 x i8> splat (i8 -1)
1064 %a = add <3 x i8> %x, <i8 42, i8 -12, i8 0>
1065 %s = sub <3 x i8> <i8 -43, i8 11, i8 -1>, %x
1066 %r = or <3 x i8> %s, %a
1071 define <2 x i17> @xor_add_sub(<2 x i17> %x) {
1072 ; CHECK-LABEL: @xor_add_sub(
1073 ; CHECK-NEXT: ret <2 x i17> splat (i17 -1)
1075 %a = add <2 x i17> %x, <i17 3000, i17 23>
1076 %s = sub <2 x i17> <i17 -3001, i17 -24>, %x
1077 %r = xor <2 x i17> %a, %s
1081 define i8 @xor_sub_add(i8 %x) {
1082 ; CHECK-LABEL: @xor_sub_add(
1083 ; CHECK-NEXT: ret i8 -1
1093 define i8 @and_add_sub_wrong_const(i8 %x) {
1094 ; CHECK-LABEL: @and_add_sub_wrong_const(
1095 ; CHECK-NEXT: [[A:%.*]] = add i8 [[X:%.*]], 6
1096 ; CHECK-NEXT: [[S:%.*]] = sub i8 -6, [[X]]
1097 ; CHECK-NEXT: [[R:%.*]] = and i8 [[A]], [[S]]
1098 ; CHECK-NEXT: ret i8 [[R]]
1108 define i8 @or_add_sub_wrong_var(i8 %x, i8 %y) {
1109 ; CHECK-LABEL: @or_add_sub_wrong_var(
1110 ; CHECK-NEXT: [[A:%.*]] = add i8 [[X:%.*]], 5
1111 ; CHECK-NEXT: [[S:%.*]] = sub i8 -6, [[Y:%.*]]
1112 ; CHECK-NEXT: [[R:%.*]] = or i8 [[A]], [[S]]
1113 ; CHECK-NEXT: ret i8 [[R]]
1123 define i8 @xor_add_sub_wrong_op(i8 %x) {
1124 ; CHECK-LABEL: @xor_add_sub_wrong_op(
1125 ; CHECK-NEXT: [[A:%.*]] = add i8 [[X:%.*]], 5
1126 ; CHECK-NEXT: [[S:%.*]] = sub i8 [[X]], -6
1127 ; CHECK-NEXT: [[R:%.*]] = xor i8 [[A]], [[S]]
1128 ; CHECK-NEXT: ret i8 [[R]]
1136 ; `and` isn't needed if it doesn't actually change any bits.
1137 define i8 @noop_and_t0(i8 %x) {
1138 ; CHECK-LABEL: @noop_and_t0(
1139 ; CHECK-NEXT: [[A:%.*]] = shl i8 [[X:%.*]], 3
1140 ; CHECK-NEXT: [[B:%.*]] = lshr i8 [[A]], 2
1141 ; CHECK-NEXT: [[R:%.*]] = and i8 [[B]], 62
1142 ; CHECK-NEXT: ret i8 [[R]]
1149 define i8 @noop_and_t1(i8 %x) {
1150 ; CHECK-LABEL: @noop_and_t1(
1151 ; CHECK-NEXT: [[A:%.*]] = shl i8 [[X:%.*]], 3
1152 ; CHECK-NEXT: [[B:%.*]] = lshr i8 [[A]], 2
1153 ; CHECK-NEXT: [[R:%.*]] = and i8 [[B]], 126
1154 ; CHECK-NEXT: ret i8 [[R]]
1162 ; hidden simplifydemandedbits constant.
1163 define i8 @noop_and_t2(i8 %x) {
1164 ; CHECK-LABEL: @noop_and_t2(
1165 ; CHECK-NEXT: [[A:%.*]] = and i8 [[X:%.*]], 2
1166 ; CHECK-NEXT: [[B:%.*]] = or i8 [[A]], 127
1167 ; CHECK-NEXT: [[C:%.*]] = and i8 [[B]], 62
1168 ; CHECK-NEXT: ret i8 [[C]]