1 ; RUN: opt -passes=loop-vectorize < %s -S -o - | FileCheck %s --check-prefixes=CHECK,CHECK-2,CHECK-NO4
2 ; RUN: opt -passes=loop-vectorize -mve-max-interleave-factor=1 < %s -S -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO2,CHECK-NO4
3 ; RUN: opt -passes=loop-vectorize -mve-max-interleave-factor=2 < %s -S -o - | FileCheck %s --check-prefixes=CHECK,CHECK-2,CHECK-NO4
4 ; RUN: opt -passes=loop-vectorize -mve-max-interleave-factor=4 < %s -S -o - | FileCheck %s --check-prefixes=CHECK,CHECK-2,CHECK-4
6 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
7 target triple = "thumbv8.1m.main-none-none-eabi"
10 ; CHECK-2: vector.body
11 ; CHECK-NO2-NOT: vector.body
12 define void @vld2(ptr nocapture readonly %pIn, ptr nocapture %pOut, i32 %numRows, i32 %numCols, i32 %scale.coerce) #0 {
14 %tmp.0.extract.trunc = trunc i32 %scale.coerce to i16
15 %0 = bitcast i16 %tmp.0.extract.trunc to half
16 %mul = mul i32 %numCols, %numRows
17 %shr = lshr i32 %mul, 2
18 %cmp26 = icmp eq i32 %shr, 0
19 br i1 %cmp26, label %while.end, label %while.body
21 while.body: ; preds = %entry, %while.body
22 %pIn.addr.029 = phi ptr [ %add.ptr, %while.body ], [ %pIn, %entry ]
23 %pOut.addr.028 = phi ptr [ %add.ptr7, %while.body ], [ %pOut, %entry ]
24 %blkCnt.027 = phi i32 [ %dec, %while.body ], [ %shr, %entry ]
25 %1 = load half, ptr %pIn.addr.029, align 2
26 %arrayidx2 = getelementptr inbounds half, ptr %pIn.addr.029, i32 1
27 %2 = load half, ptr %arrayidx2, align 2
28 %mul3 = fmul half %1, %0
29 %mul4 = fmul half %2, %0
30 store half %mul3, ptr %pOut.addr.028, align 2
31 %arrayidx6 = getelementptr inbounds half, ptr %pOut.addr.028, i32 1
32 store half %mul4, ptr %arrayidx6, align 2
33 %add.ptr = getelementptr inbounds half, ptr %pIn.addr.029, i32 2
34 %add.ptr7 = getelementptr inbounds half, ptr %pOut.addr.028, i32 2
35 %dec = add nsw i32 %blkCnt.027, -1
36 %cmp = icmp eq i32 %dec, 0
37 br i1 %cmp, label %while.end, label %while.body
39 while.end: ; preds = %while.body, %entry
44 ; CHECK-4: vector.body
45 ; CHECK-NO4-NOT: vector.body
46 define void @vld4(ptr nocapture readonly %pIn, ptr nocapture %pOut, i32 %numRows, i32 %numCols, i32 %scale.coerce) #0 {
48 %tmp.0.extract.trunc = trunc i32 %scale.coerce to i16
49 %0 = bitcast i16 %tmp.0.extract.trunc to half
50 %mul = mul i32 %numCols, %numRows
51 %shr = lshr i32 %mul, 2
52 %cmp38 = icmp eq i32 %shr, 0
53 br i1 %cmp38, label %while.end, label %while.body
55 while.body: ; preds = %entry, %while.body
56 %pIn.addr.041 = phi ptr [ %add.ptr, %while.body ], [ %pIn, %entry ]
57 %pOut.addr.040 = phi ptr [ %add.ptr13, %while.body ], [ %pOut, %entry ]
58 %blkCnt.039 = phi i32 [ %dec, %while.body ], [ %shr, %entry ]
59 %1 = load half, ptr %pIn.addr.041, align 2
60 %arrayidx2 = getelementptr inbounds half, ptr %pIn.addr.041, i32 1
61 %2 = load half, ptr %arrayidx2, align 2
62 %arrayidx3 = getelementptr inbounds half, ptr %pIn.addr.041, i32 2
63 %3 = load half, ptr %arrayidx3, align 2
64 %arrayidx4 = getelementptr inbounds half, ptr %pIn.addr.041, i32 3
65 %4 = load half, ptr %arrayidx4, align 2
66 %mul5 = fmul half %1, %0
67 %mul6 = fmul half %2, %0
68 %mul7 = fmul half %3, %0
69 %mul8 = fmul half %4, %0
70 store half %mul5, ptr %pOut.addr.040, align 2
71 %arrayidx10 = getelementptr inbounds half, ptr %pOut.addr.040, i32 1
72 store half %mul6, ptr %arrayidx10, align 2
73 %arrayidx11 = getelementptr inbounds half, ptr %pOut.addr.040, i32 2
74 store half %mul7, ptr %arrayidx11, align 2
75 %arrayidx12 = getelementptr inbounds half, ptr %pOut.addr.040, i32 3
76 store half %mul8, ptr %arrayidx12, align 2
77 %add.ptr = getelementptr inbounds half, ptr %pIn.addr.041, i32 4
78 %add.ptr13 = getelementptr inbounds half, ptr %pOut.addr.040, i32 4
79 %dec = add nsw i32 %blkCnt.039, -1
80 %cmp = icmp eq i32 %dec, 0
81 br i1 %cmp, label %while.end, label %while.body
83 while.end: ; preds = %while.body, %entry
87 attributes #0 = { "target-features"="+armv8.1-m.main,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-crypto,-d32,-fp-armv8,-fp-armv8sp,-neon,-vfp3,-vfp3sp,-vfp4,-vfp4sp" }