1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2 ; RUN: opt -p loop-vectorize -S %s | FileCheck %s
4 target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
5 target triple = "x86_64-apple-macosx"
7 define i32 @ephemeral_load_and_compare_iv_used_outside(ptr %start, ptr %end) #0 {
8 ; CHECK-LABEL: define i32 @ephemeral_load_and_compare_iv_used_outside(
9 ; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0:[0-9]+]] {
10 ; CHECK-NEXT: [[ENTRY:.*]]:
11 ; CHECK-NEXT: br label %[[LOOP:.*]]
13 ; CHECK-NEXT: [[IV:%.*]] = phi ptr [ [[START]], %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
14 ; CHECK-NEXT: [[IV_NEXT]] = getelementptr nusw i8, ptr [[IV]], i64 -8
15 ; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[IV]], align 4
16 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[L1]], 0
17 ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
18 ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq ptr [[IV]], [[END]]
19 ; CHECK-NEXT: br i1 [[CMP_NOT]], label %[[EXIT:.*]], label %[[LOOP]]
21 ; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi ptr [ [[IV]], %[[LOOP]] ]
22 ; CHECK-NEXT: [[FINAL_LOAD:%.*]] = load i32, ptr [[IV_LCSSA]], align 4
23 ; CHECK-NEXT: ret i32 [[FINAL_LOAD]]
29 %iv = phi ptr [ %start, %entry ],[ %iv.next, %loop ]
30 %iv.next = getelementptr nusw i8, ptr %iv, i64 -8
31 %l1 = load i32, ptr %iv, align 4
32 %cmp = icmp ne i32 %l1, 0
33 call void @llvm.assume(i1 %cmp)
34 %cmp.not = icmp eq ptr %iv, %end
35 br i1 %cmp.not, label %exit, label %loop
38 %final.load = load i32, ptr %iv, align 4
42 define i32 @ephemeral_load_and_compare_another_load_used_outside(ptr %start, ptr %end) #0 {
43 ; CHECK-LABEL: define i32 @ephemeral_load_and_compare_another_load_used_outside(
44 ; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
45 ; CHECK-NEXT: [[ENTRY:.*]]:
46 ; CHECK-NEXT: br label %[[LOOP:.*]]
48 ; CHECK-NEXT: [[IV:%.*]] = phi ptr [ [[START]], %[[ENTRY]] ], [ [[IV_NEXT2:%.*]], %[[LOOP]] ]
49 ; CHECK-NEXT: [[IV_NEXT2]] = getelementptr nusw i8, ptr [[IV]], i64 -8
50 ; CHECK-NEXT: [[L1:%.*]] = load ptr, ptr [[END]], align 8
51 ; CHECK-NEXT: [[L2:%.*]] = load i32, ptr [[L1]], align 4
52 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[L2]], 0
53 ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
54 ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq ptr [[IV]], [[END]]
55 ; CHECK-NEXT: br i1 [[CMP_NOT]], label %[[EXIT:.*]], label %[[LOOP]]
57 ; CHECK-NEXT: [[L1_LCSSA:%.*]] = phi ptr [ [[L1]], %[[LOOP]] ]
58 ; CHECK-NEXT: [[FINAL_LOAD:%.*]] = load i32, ptr [[L1_LCSSA]], align 4
59 ; CHECK-NEXT: ret i32 [[FINAL_LOAD]]
65 %iv = phi ptr [ %start, %entry ], [ %iv.next2, %loop ]
66 %iv.next2 = getelementptr nusw i8, ptr %iv, i64 -8
67 %l1 = load ptr, ptr %end, align 8
68 %l2 = load i32, ptr %l1, align 4
69 %cmp = icmp ne i32 %l2, 0
70 call void @llvm.assume(i1 %cmp)
71 %cmp.not = icmp eq ptr %iv, %end
72 br i1 %cmp.not, label %exit, label %loop
75 %final.load = load i32, ptr %l1, align 4
79 declare void @llvm.assume(i1 noundef)
81 attributes #0 = { "target-cpu"="skylake-avx512" }