| blob | fd89c8b019341560492f86c78dccf1daea5b7a2a |
1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2 ; RUN: opt -p loop-vectorize -S %s | FileCheck %s
4 target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
5 target triple = "x86_64-apple-macosx10.15.0"
7 define void @test_free_instructions_feeding_geps_for_interleave_groups(ptr noalias %p.invar, ptr noalias %dst.1, ptr noalias %dst.2) {
8 ; CHECK-LABEL: define void @test_free_instructions_feeding_geps_for_interleave_groups(
9 ; CHECK-SAME: ptr noalias [[P_INVAR:%.*]], ptr noalias [[DST_1:%.*]], ptr noalias [[DST_2:%.*]]) {
10 ; CHECK-NEXT: [[ENTRY:.*]]:
11 ; CHECK-NEXT: br i1 true, label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
12 ; CHECK: [[VECTOR_SCEVCHECK]]:
13 ; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST_1]], i64 8
14 ; CHECK-NEXT: [[MUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 -1)
15 ; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i64, i1 } [[MUL]], 0
16 ; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i64, i1 } [[MUL]], 1
17 ; CHECK-NEXT: [[TMP0:%.*]] = sub i64 0, [[MUL_RESULT]]
18 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[MUL_RESULT]]
19 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ult ptr [[TMP1]], [[SCEVGEP]]
20 ; CHECK-NEXT: [[TMP3:%.*]] = or i1 [[TMP2]], [[MUL_OVERFLOW]]
21 ; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[DST_1]], i64 12
22 ; CHECK-NEXT: [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 -1)
23 ; CHECK-NEXT: [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
24 ; CHECK-NEXT: [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
25 ; CHECK-NEXT: [[TMP4:%.*]] = sub i64 0, [[MUL_RESULT3]]
26 ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[SCEVGEP1]], i64 [[MUL_RESULT3]]
27 ; CHECK-NEXT: [[TMP6:%.*]] = icmp ult ptr [[TMP5]], [[SCEVGEP1]]
28 ; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP6]], [[MUL_OVERFLOW4]]
29 ; CHECK-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[DST_1]], i64 4
30 ; CHECK-NEXT: [[MUL6:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 -1)
31 ; CHECK-NEXT: [[MUL_RESULT7:%.*]] = extractvalue { i64, i1 } [[MUL6]], 0
32 ; CHECK-NEXT: [[MUL_OVERFLOW8:%.*]] = extractvalue { i64, i1 } [[MUL6]], 1
33 ; CHECK-NEXT: [[TMP8:%.*]] = sub i64 0, [[MUL_RESULT7]]
34 ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[SCEVGEP5]], i64 [[MUL_RESULT7]]
35 ; CHECK-NEXT: [[TMP10:%.*]] = icmp ult ptr [[TMP9]], [[SCEVGEP5]]
36 ; CHECK-NEXT: [[TMP11:%.*]] = or i1 [[TMP10]], [[MUL_OVERFLOW8]]
37 ; CHECK-NEXT: [[MUL9:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 -1)
38 ; CHECK-NEXT: [[MUL_RESULT10:%.*]] = extractvalue { i64, i1 } [[MUL9]], 0
39 ; CHECK-NEXT: [[MUL_OVERFLOW11:%.*]] = extractvalue { i64, i1 } [[MUL9]], 1
40 ; CHECK-NEXT: [[TMP12:%.*]] = sub i64 0, [[MUL_RESULT10]]
41 ; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[DST_1]], i64 [[MUL_RESULT10]]
42 ; CHECK-NEXT: [[TMP14:%.*]] = icmp ult ptr [[TMP13]], [[DST_1]]
43 ; CHECK-NEXT: [[TMP15:%.*]] = or i1 [[TMP14]], [[MUL_OVERFLOW11]]
44 ; CHECK-NEXT: [[SCEVGEP12:%.*]] = getelementptr i8, ptr [[DST_2]], i64 8
45 ; CHECK-NEXT: [[MUL13:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 -1)
46 ; CHECK-NEXT: [[MUL_RESULT14:%.*]] = extractvalue { i64, i1 } [[MUL13]], 0
47 ; CHECK-NEXT: [[MUL_OVERFLOW15:%.*]] = extractvalue { i64, i1 } [[MUL13]], 1
48 ; CHECK-NEXT: [[TMP16:%.*]] = sub i64 0, [[MUL_RESULT14]]
49 ; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[SCEVGEP12]], i64 [[MUL_RESULT14]]
50 ; CHECK-NEXT: [[TMP18:%.*]] = icmp ult ptr [[TMP17]], [[SCEVGEP12]]
51 ; CHECK-NEXT: [[TMP19:%.*]] = or i1 [[TMP18]], [[MUL_OVERFLOW15]]
52 ; CHECK-NEXT: [[SCEVGEP16:%.*]] = getelementptr i8, ptr [[DST_2]], i64 12
53 ; CHECK-NEXT: [[MUL17:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 -1)
54 ; CHECK-NEXT: [[MUL_RESULT18:%.*]] = extractvalue { i64, i1 } [[MUL17]], 0
55 ; CHECK-NEXT: [[MUL_OVERFLOW19:%.*]] = extractvalue { i64, i1 } [[MUL17]], 1
56 ; CHECK-NEXT: [[TMP20:%.*]] = sub i64 0, [[MUL_RESULT18]]
57 ; CHECK-NEXT: [[TMP21:%.*]] = getelementptr i8, ptr [[SCEVGEP16]], i64 [[MUL_RESULT18]]
58 ; CHECK-NEXT: [[TMP22:%.*]] = icmp ult ptr [[TMP21]], [[SCEVGEP16]]
59 ; CHECK-NEXT: [[TMP23:%.*]] = or i1 [[TMP22]], [[MUL_OVERFLOW19]]
60 ; CHECK-NEXT: [[SCEVGEP20:%.*]] = getelementptr i8, ptr [[DST_2]], i64 4
61 ; CHECK-NEXT: [[MUL21:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 -1)
62 ; CHECK-NEXT: [[MUL_RESULT22:%.*]] = extractvalue { i64, i1 } [[MUL21]], 0
63 ; CHECK-NEXT: [[MUL_OVERFLOW23:%.*]] = extractvalue { i64, i1 } [[MUL21]], 1
64 ; CHECK-NEXT: [[TMP24:%.*]] = sub i64 0, [[MUL_RESULT22]]
65 ; CHECK-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[SCEVGEP20]], i64 [[MUL_RESULT22]]
66 ; CHECK-NEXT: [[TMP26:%.*]] = icmp ult ptr [[TMP25]], [[SCEVGEP20]]
67 ; CHECK-NEXT: [[TMP27:%.*]] = or i1 [[TMP26]], [[MUL_OVERFLOW23]]
68 ; CHECK-NEXT: [[MUL24:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 -1)
69 ; CHECK-NEXT: [[MUL_RESULT25:%.*]] = extractvalue { i64, i1 } [[MUL24]], 0
70 ; CHECK-NEXT: [[MUL_OVERFLOW26:%.*]] = extractvalue { i64, i1 } [[MUL24]], 1
71 ; CHECK-NEXT: [[TMP28:%.*]] = sub i64 0, [[MUL_RESULT25]]
72 ; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[DST_2]], i64 [[MUL_RESULT25]]
73 ; CHECK-NEXT: [[TMP30:%.*]] = icmp ult ptr [[TMP29]], [[DST_2]]
74 ; CHECK-NEXT: [[TMP31:%.*]] = or i1 [[TMP30]], [[MUL_OVERFLOW26]]
75 ; CHECK-NEXT: [[TMP32:%.*]] = or i1 [[TMP3]], [[TMP7]]
76 ; CHECK-NEXT: [[TMP33:%.*]] = or i1 [[TMP32]], [[TMP11]]
77 ; CHECK-NEXT: [[TMP34:%.*]] = or i1 [[TMP33]], [[TMP15]]
78 ; CHECK-NEXT: [[TMP35:%.*]] = or i1 [[TMP34]], [[TMP19]]
79 ; CHECK-NEXT: [[TMP36:%.*]] = or i1 [[TMP35]], [[TMP23]]
80 ; CHECK-NEXT: [[TMP37:%.*]] = or i1 [[TMP36]], [[TMP27]]
81 ; CHECK-NEXT: [[TMP38:%.*]] = or i1 [[TMP37]], [[TMP31]]
82 ; CHECK-NEXT: br i1 [[TMP38]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
83 ; CHECK: [[VECTOR_PH]]:
84 ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
85 ; CHECK: [[VECTOR_BODY]]:
86 ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
87 ; CHECK-NEXT: [[TMP39:%.*]] = add i64 [[INDEX]], 0
88 ; CHECK-NEXT: [[TMP40:%.*]] = load float, ptr [[P_INVAR]], align 4
89 ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x float> poison, float [[TMP40]], i64 0
90 ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x float> [[BROADCAST_SPLATINSERT]], <2 x float> poison, <2 x i32> zeroinitializer
91 ; CHECK-NEXT: [[TMP41:%.*]] = shl i64 [[TMP39]], 2
92 ; CHECK-NEXT: [[TMP44:%.*]] = getelementptr float, ptr [[DST_1]], i64 [[TMP41]]
93 ; CHECK-NEXT: [[TMP42:%.*]] = load float, ptr [[P_INVAR]], align 4
94 ; CHECK-NEXT: [[BROADCAST_SPLATINSERT27:%.*]] = insertelement <2 x float> poison, float [[TMP42]], i64 0
95 ; CHECK-NEXT: [[BROADCAST_SPLAT28:%.*]] = shufflevector <2 x float> [[BROADCAST_SPLATINSERT27]], <2 x float> poison, <2 x i32> zeroinitializer
96 ; CHECK-NEXT: [[TMP46:%.*]] = shufflevector <2 x float> [[BROADCAST_SPLAT]], <2 x float> [[BROADCAST_SPLAT28]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
97 ; CHECK-NEXT: [[TMP47:%.*]] = shufflevector <4 x float> [[TMP46]], <4 x float> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
98 ; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x float> [[TMP47]], <8 x float> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
99 ; CHECK-NEXT: store <8 x float> [[INTERLEAVED_VEC]], ptr [[TMP44]], align 4
100 ; CHECK-NEXT: [[TMP48:%.*]] = load float, ptr [[P_INVAR]], align 4
101 ; CHECK-NEXT: [[BROADCAST_SPLATINSERT29:%.*]] = insertelement <2 x float> poison, float [[TMP48]], i64 0
102 ; CHECK-NEXT: [[BROADCAST_SPLAT30:%.*]] = shufflevector <2 x float> [[BROADCAST_SPLATINSERT29]], <2 x float> poison, <2 x i32> zeroinitializer
103 ; CHECK-NEXT: [[TMP49:%.*]] = getelementptr float, ptr [[DST_2]], i64 [[TMP41]]
104 ; CHECK-NEXT: [[BROADCAST_SPLAT36:%.*]] = shufflevector <2 x float> [[BROADCAST_SPLAT30]], <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
105 ; CHECK-NEXT: [[TMP51:%.*]] = shufflevector <4 x float> [[BROADCAST_SPLAT36]], <4 x float> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
106 ; CHECK-NEXT: [[INTERLEAVED_VEC31:%.*]] = shufflevector <8 x float> [[TMP51]], <8 x float> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
107 ; CHECK-NEXT: store <8 x float> [[INTERLEAVED_VEC31]], ptr [[TMP49]], align 4
108 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
109 ; CHECK-NEXT: [[TMP53:%.*]] = icmp eq i64 [[INDEX_NEXT]], 0
110 ; CHECK-NEXT: br i1 [[TMP53]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
111 ; CHECK: [[MIDDLE_BLOCK]]:
112 ; CHECK-NEXT: br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]]
113 ; CHECK: [[SCALAR_PH]]:
114 ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 0, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
115 ; CHECK-NEXT: br label %[[LOOP:.*]]
116 ; CHECK: [[LOOP]]:
117 ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
118 ; CHECK-NEXT: [[L_0:%.*]] = load float, ptr [[P_INVAR]], align 4
119 ; CHECK-NEXT: [[IV_MUL:%.*]] = shl i64 [[IV]], 2
120 ; CHECK-NEXT: [[GEP_DST_19:%.*]] = getelementptr float, ptr [[DST_1]], i64 [[IV_MUL]]
121 ; CHECK-NEXT: store float [[L_0]], ptr [[GEP_DST_19]], align 4
122 ; CHECK-NEXT: [[L_1:%.*]] = load float, ptr [[P_INVAR]], align 4
123 ; CHECK-NEXT: [[ADD_1:%.*]] = or disjoint i64 [[IV_MUL]], 1
124 ; CHECK-NEXT: [[GEP_DST_119:%.*]] = getelementptr float, ptr [[DST_1]], i64 [[ADD_1]]
125 ; CHECK-NEXT: store float [[L_1]], ptr [[GEP_DST_119]], align 4
126 ; CHECK-NEXT: [[ADD_2:%.*]] = or disjoint i64 [[IV_MUL]], 2
127 ; CHECK-NEXT: [[GEP_DST_129:%.*]] = getelementptr float, ptr [[DST_1]], i64 [[ADD_2]]
128 ; CHECK-NEXT: store float 0.000000e+00, ptr [[GEP_DST_129]], align 4
129 ; CHECK-NEXT: [[ADD_3:%.*]] = or disjoint i64 [[IV_MUL]], 3
130 ; CHECK-NEXT: [[GEP_DST_140:%.*]] = getelementptr float, ptr [[DST_1]], i64 [[ADD_3]]
131 ; CHECK-NEXT: store float 0.000000e+00, ptr [[GEP_DST_140]], align 4
132 ; CHECK-NEXT: [[L_2:%.*]] = load float, ptr [[P_INVAR]], align 4
133 ; CHECK-NEXT: [[GEP_DST_247:%.*]] = getelementptr float, ptr [[DST_2]], i64 [[IV_MUL]]
134 ; CHECK-NEXT: store float [[L_2]], ptr [[GEP_DST_247]], align 4
135 ; CHECK-NEXT: [[GEP_DST_255:%.*]] = getelementptr float, ptr [[DST_2]], i64 [[ADD_1]]
136 ; CHECK-NEXT: store float 0.000000e+00, ptr [[GEP_DST_255]], align 4
137 ; CHECK-NEXT: [[GEP_DST_265:%.*]] = getelementptr float, ptr [[DST_2]], i64 [[ADD_2]]
138 ; CHECK-NEXT: store float 0.000000e+00, ptr [[GEP_DST_265]], align 4
139 ; CHECK-NEXT: [[GEP_DST_276:%.*]] = getelementptr float, ptr [[DST_2]], i64 [[ADD_3]]
140 ; CHECK-NEXT: store float 0.000000e+00, ptr [[GEP_DST_276]], align 4
141 ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
142 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 0
143 ; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
144 ; CHECK: [[EXIT]]:
145 ; CHECK-NEXT: ret void
146 ;
147 entry:
148 br label %loop
150 loop:
151 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
152 %l.0 = load float, ptr %p.invar, align 4
153 %iv.mul = shl i64 %iv, 2
154 %gep.dst.19 = getelementptr float, ptr %dst.1, i64 %iv.mul
155 store float %l.0, ptr %gep.dst.19, align 4
156 %l.1 = load float, ptr %p.invar, align 4
157 %add.1 = or disjoint i64 %iv.mul, 1
158 %gep.dst.119 = getelementptr float, ptr %dst.1, i64 %add.1
159 store float %l.1, ptr %gep.dst.119, align 4
160 %add.2 = or disjoint i64 %iv.mul, 2
161 %gep.dst.129 = getelementptr float, ptr %dst.1, i64 %add.2
162 store float 0.000000e+00, ptr %gep.dst.129, align 4
163 %add.3 = or disjoint i64 %iv.mul, 3
164 %gep.dst.140 = getelementptr float, ptr %dst.1, i64 %add.3
165 store float 0.000000e+00, ptr %gep.dst.140, align 4
166 %l.2 = load float, ptr %p.invar, align 4
167 %gep.dst.247 = getelementptr float, ptr %dst.2, i64 %iv.mul
168 store float %l.2, ptr %gep.dst.247, align 4
169 %gep.dst.255 = getelementptr float, ptr %dst.2, i64 %add.1
170 store float 0.000000e+00, ptr %gep.dst.255, align 4
171 %gep.dst.265 = getelementptr float, ptr %dst.2, i64 %add.2
172 store float 0.000000e+00, ptr %gep.dst.265, align 4
173 %gep.dst.276 = getelementptr float, ptr %dst.2, i64 %add.3
174 store float 0.000000e+00, ptr %gep.dst.276, align 4
175 %iv.next = add i64 %iv, 1
176 %ec = icmp eq i64 %iv.next, 0
177 br i1 %ec, label %exit, label %loop
179 exit:
180 ret void
181 }
183 define void @geps_feeding_interleave_groups_with_reuse(ptr %arg, i64 %arg1, ptr %arg2) #0 {
184 ; CHECK-LABEL: define void @geps_feeding_interleave_groups_with_reuse(
185 ; CHECK-SAME: ptr [[ARG:%.*]], i64 [[ARG1:%.*]], ptr [[ARG2:%.*]]) #[[ATTR0:[0-9]+]] {
186 ; CHECK-NEXT: [[ENTRY:.*]]:
187 ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[ARG1]], 1
188 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 54
189 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
190 ; CHECK: [[VECTOR_SCEVCHECK]]:
191 ; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[ARG2]], i64 8
192 ; CHECK-NEXT: [[MUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 [[ARG1]])
193 ; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i64, i1 } [[MUL]], 0
194 ; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i64, i1 } [[MUL]], 1
195 ; CHECK-NEXT: [[TMP1:%.*]] = sub i64 0, [[MUL_RESULT]]
196 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[MUL_RESULT]]
197 ; CHECK-NEXT: [[TMP3:%.*]] = icmp ult ptr [[TMP2]], [[SCEVGEP]]
198 ; CHECK-NEXT: [[TMP4:%.*]] = or i1 [[TMP3]], [[MUL_OVERFLOW]]
199 ; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[ARG2]], i64 12
200 ; CHECK-NEXT: [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 [[ARG1]])
201 ; CHECK-NEXT: [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
202 ; CHECK-NEXT: [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
203 ; CHECK-NEXT: [[TMP5:%.*]] = sub i64 0, [[MUL_RESULT3]]
204 ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[SCEVGEP1]], i64 [[MUL_RESULT3]]
205 ; CHECK-NEXT: [[TMP7:%.*]] = icmp ult ptr [[TMP6]], [[SCEVGEP1]]
206 ; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW4]]
207 ; CHECK-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[ARG2]], i64 4
208 ; CHECK-NEXT: [[MUL6:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 [[ARG1]])
209 ; CHECK-NEXT: [[MUL_RESULT7:%.*]] = extractvalue { i64, i1 } [[MUL6]], 0
210 ; CHECK-NEXT: [[MUL_OVERFLOW8:%.*]] = extractvalue { i64, i1 } [[MUL6]], 1
211 ; CHECK-NEXT: [[TMP9:%.*]] = sub i64 0, [[MUL_RESULT7]]
212 ; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[SCEVGEP5]], i64 [[MUL_RESULT7]]
213 ; CHECK-NEXT: [[TMP11:%.*]] = icmp ult ptr [[TMP10]], [[SCEVGEP5]]
214 ; CHECK-NEXT: [[TMP12:%.*]] = or i1 [[TMP11]], [[MUL_OVERFLOW8]]
215 ; CHECK-NEXT: [[MUL9:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 [[ARG1]])
216 ; CHECK-NEXT: [[MUL_RESULT10:%.*]] = extractvalue { i64, i1 } [[MUL9]], 0
217 ; CHECK-NEXT: [[MUL_OVERFLOW11:%.*]] = extractvalue { i64, i1 } [[MUL9]], 1
218 ; CHECK-NEXT: [[TMP13:%.*]] = sub i64 0, [[MUL_RESULT10]]
219 ; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[ARG2]], i64 [[MUL_RESULT10]]
220 ; CHECK-NEXT: [[TMP15:%.*]] = icmp ult ptr [[TMP14]], [[ARG2]]
221 ; CHECK-NEXT: [[TMP16:%.*]] = or i1 [[TMP15]], [[MUL_OVERFLOW11]]
222 ; CHECK-NEXT: [[TMP17:%.*]] = or i1 [[TMP4]], [[TMP8]]
223 ; CHECK-NEXT: [[TMP18:%.*]] = or i1 [[TMP17]], [[TMP12]]
224 ; CHECK-NEXT: [[TMP19:%.*]] = or i1 [[TMP18]], [[TMP16]]
225 ; CHECK-NEXT: br i1 [[TMP19]], label %[[SCALAR_PH]], label %[[VECTOR_MEMCHECK:.*]]
226 ; CHECK: [[VECTOR_MEMCHECK]]:
227 ; CHECK-NEXT: [[TMP20:%.*]] = shl i64 [[ARG1]], 4
228 ; CHECK-NEXT: [[TMP21:%.*]] = add i64 [[TMP20]], 16
229 ; CHECK-NEXT: [[SCEVGEP12:%.*]] = getelementptr i8, ptr [[ARG2]], i64 [[TMP21]]
230 ; CHECK-NEXT: [[TMP22:%.*]] = shl i64 [[ARG1]], 5
231 ; CHECK-NEXT: [[TMP23:%.*]] = add i64 [[TMP22]], 32
232 ; CHECK-NEXT: [[SCEVGEP13:%.*]] = getelementptr i8, ptr [[ARG]], i64 [[TMP23]]
233 ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[ARG2]], [[SCEVGEP13]]
234 ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[ARG]], [[SCEVGEP12]]
235 ; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
236 ; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
237 ; CHECK: [[VECTOR_PH]]:
238 ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 2
239 ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
240 ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
241 ; CHECK: [[VECTOR_BODY]]:
242 ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
243 ; CHECK-NEXT: [[TMP24:%.*]] = add i64 [[INDEX]], 0
244 ; CHECK-NEXT: [[TMP25:%.*]] = shl i64 [[TMP24]], 5
245 ; CHECK-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[ARG]], i64 [[TMP25]]
246 ; CHECK-NEXT: [[TMP27:%.*]] = shl i64 [[TMP24]], 4
247 ; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[ARG2]], i64 [[TMP27]]
248 ; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <16 x float>, ptr [[TMP26]], align 4
249 ; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <16 x float> [[WIDE_VEC]], <16 x float> poison, <2 x i32> <i32 0, i32 8>
250 ; CHECK-NEXT: [[STRIDED_VEC14:%.*]] = shufflevector <16 x float> [[WIDE_VEC]], <16 x float> poison, <2 x i32> <i32 1, i32 9>
251 ; CHECK-NEXT: [[STRIDED_VEC15:%.*]] = shufflevector <16 x float> [[WIDE_VEC]], <16 x float> poison, <2 x i32> <i32 2, i32 10>
252 ; CHECK-NEXT: [[STRIDED_VEC16:%.*]] = shufflevector <16 x float> [[WIDE_VEC]], <16 x float> poison, <2 x i32> <i32 3, i32 11>
253 ; CHECK-NEXT: [[STRIDED_VEC17:%.*]] = shufflevector <16 x float> [[WIDE_VEC]], <16 x float> poison, <2 x i32> <i32 4, i32 12>
254 ; CHECK-NEXT: [[STRIDED_VEC18:%.*]] = shufflevector <16 x float> [[WIDE_VEC]], <16 x float> poison, <2 x i32> <i32 5, i32 13>
255 ; CHECK-NEXT: [[STRIDED_VEC19:%.*]] = shufflevector <16 x float> [[WIDE_VEC]], <16 x float> poison, <2 x i32> <i32 6, i32 14>
256 ; CHECK-NEXT: [[STRIDED_VEC20:%.*]] = shufflevector <16 x float> [[WIDE_VEC]], <16 x float> poison, <2 x i32> <i32 7, i32 15>
257 ; CHECK-NEXT: [[TMP30:%.*]] = fadd <2 x float> [[STRIDED_VEC]], [[STRIDED_VEC17]]
258 ; CHECK-NEXT: [[TMP31:%.*]] = fmul <2 x float> [[TMP30]], zeroinitializer
259 ; CHECK-NEXT: [[TMP32:%.*]] = fadd <2 x float> [[STRIDED_VEC14]], [[STRIDED_VEC18]]
260 ; CHECK-NEXT: [[TMP33:%.*]] = fmul <2 x float> [[TMP32]], zeroinitializer
261 ; CHECK-NEXT: [[TMP34:%.*]] = fadd <2 x float> [[STRIDED_VEC15]], [[STRIDED_VEC19]]
262 ; CHECK-NEXT: [[TMP35:%.*]] = fmul <2 x float> [[TMP34]], zeroinitializer
263 ; CHECK-NEXT: [[TMP36:%.*]] = fadd <2 x float> [[STRIDED_VEC16]], [[STRIDED_VEC20]]
264 ; CHECK-NEXT: [[TMP37:%.*]] = fmul <2 x float> [[TMP36]], zeroinitializer
265 ; CHECK-NEXT: [[TMP40:%.*]] = shufflevector <2 x float> [[TMP31]], <2 x float> [[TMP33]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
266 ; CHECK-NEXT: [[TMP41:%.*]] = shufflevector <2 x float> [[TMP35]], <2 x float> [[TMP37]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
267 ; CHECK-NEXT: [[TMP42:%.*]] = shufflevector <4 x float> [[TMP40]], <4 x float> [[TMP41]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
268 ; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x float> [[TMP42]], <8 x float> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
269 ; CHECK-NEXT: store <8 x float> [[INTERLEAVED_VEC]], ptr [[TMP28]], align 4
270 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
271 ; CHECK-NEXT: [[TMP43:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
272 ; CHECK-NEXT: br i1 [[TMP43]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
273 ; CHECK: [[MIDDLE_BLOCK]]:
274 ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
275 ; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
276 ; CHECK: [[SCALAR_PH]]:
277 ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
278 ; CHECK-NEXT: br label %[[LOOP:.*]]
279 ; CHECK: [[LOOP]]:
280 ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
281 ; CHECK-NEXT: [[SHL_IV_5:%.*]] = shl i64 [[IV]], 5
282 ; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr i8, ptr [[ARG]], i64 [[SHL_IV_5]]
283 ; CHECK-NEXT: [[ADD_5:%.*]] = or disjoint i64 [[SHL_IV_5]], 16
284 ; CHECK-NEXT: [[GEP_2:%.*]] = getelementptr i8, ptr [[ARG]], i64 [[ADD_5]]
285 ; CHECK-NEXT: [[SHL_IV_4:%.*]] = shl i64 [[IV]], 4
286 ; CHECK-NEXT: [[GEP_3:%.*]] = getelementptr i8, ptr [[ARG2]], i64 [[SHL_IV_4]]
287 ; CHECK-NEXT: [[L_1:%.*]] = load float, ptr [[GEP_1]], align 4
288 ; CHECK-NEXT: [[L_2:%.*]] = load float, ptr [[GEP_2]], align 4
289 ; CHECK-NEXT: [[ADD_1:%.*]] = fadd float [[L_1]], [[L_2]]
290 ; CHECK-NEXT: [[MUL_1:%.*]] = fmul float [[ADD_1]], 0.000000e+00
291 ; CHECK-NEXT: store float [[MUL_1]], ptr [[GEP_3]], align 4
292 ; CHECK-NEXT: [[GEP_4:%.*]] = getelementptr i8, ptr [[GEP_1]], i64 4
293 ; CHECK-NEXT: [[L_3:%.*]] = load float, ptr [[GEP_4]], align 4
294 ; CHECK-NEXT: [[GEP_5:%.*]] = getelementptr i8, ptr [[GEP_2]], i64 4
295 ; CHECK-NEXT: [[L_4:%.*]] = load float, ptr [[GEP_5]], align 4
296 ; CHECK-NEXT: [[ADD_2:%.*]] = fadd float [[L_3]], [[L_4]]
297 ; CHECK-NEXT: [[MUL_2:%.*]] = fmul float [[ADD_2]], 0.000000e+00
298 ; CHECK-NEXT: [[GEP_6:%.*]] = getelementptr i8, ptr [[GEP_3]], i64 4
299 ; CHECK-NEXT: store float [[MUL_2]], ptr [[GEP_6]], align 4
300 ; CHECK-NEXT: [[GEP_7:%.*]] = getelementptr i8, ptr [[GEP_1]], i64 8
301 ; CHECK-NEXT: [[L_5:%.*]] = load float, ptr [[GEP_7]], align 4
302 ; CHECK-NEXT: [[GEP_8:%.*]] = getelementptr i8, ptr [[GEP_2]], i64 8
303 ; CHECK-NEXT: [[L_6:%.*]] = load float, ptr [[GEP_8]], align 4
304 ; CHECK-NEXT: [[ADD_3:%.*]] = fadd float [[L_5]], [[L_6]]
305 ; CHECK-NEXT: [[MUL_3:%.*]] = fmul float [[ADD_3]], 0.000000e+00
306 ; CHECK-NEXT: [[GEP_9:%.*]] = getelementptr i8, ptr [[GEP_3]], i64 8
307 ; CHECK-NEXT: store float [[MUL_3]], ptr [[GEP_9]], align 4
308 ; CHECK-NEXT: [[I27:%.*]] = getelementptr i8, ptr [[GEP_1]], i64 12
309 ; CHECK-NEXT: [[L_7:%.*]] = load float, ptr [[I27]], align 4
310 ; CHECK-NEXT: [[GEP_10:%.*]] = getelementptr i8, ptr [[GEP_2]], i64 12
311 ; CHECK-NEXT: [[L_8:%.*]] = load float, ptr [[GEP_10]], align 4
312 ; CHECK-NEXT: [[ADD_4:%.*]] = fadd float [[L_7]], [[L_8]]
313 ; CHECK-NEXT: [[MUL_4:%.*]] = fmul float [[ADD_4]], 0.000000e+00
314 ; CHECK-NEXT: [[GEP_11:%.*]] = getelementptr i8, ptr [[GEP_3]], i64 12
315 ; CHECK-NEXT: store float [[MUL_4]], ptr [[GEP_11]], align 4
316 ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
317 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[ARG1]]
318 ; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
319 ; CHECK: [[EXIT]]:
320 ; CHECK-NEXT: ret void
321 ;
322 entry:
323 br label %loop
325 loop:
326 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
327 %shl.iv.5 = shl i64 %iv, 5
328 %gep.1 = getelementptr i8, ptr %arg, i64 %shl.iv.5
329 %add.5 = or disjoint i64 %shl.iv.5, 16
330 %gep.2 = getelementptr i8, ptr %arg, i64 %add.5
331 %shl.iv.4 = shl i64 %iv, 4
332 %gep.3 = getelementptr i8, ptr %arg2, i64 %shl.iv.4
333 %l.1 = load float, ptr %gep.1, align 4
334 %l.2 = load float, ptr %gep.2, align 4
335 %add.1 = fadd float %l.1, %l.2
336 %mul.1 = fmul float %add.1, 0.000000e+00
337 store float %mul.1, ptr %gep.3, align 4
338 %gep.4 = getelementptr i8, ptr %gep.1, i64 4
339 %l.3 = load float, ptr %gep.4, align 4
340 %gep.5 = getelementptr i8, ptr %gep.2, i64 4
341 %l.4 = load float, ptr %gep.5, align 4
342 %add.2 = fadd float %l.3, %l.4
343 %mul.2 = fmul float %add.2, 0.000000e+00
344 %gep.6 = getelementptr i8, ptr %gep.3, i64 4
345 store float %mul.2, ptr %gep.6, align 4
346 %gep.7 = getelementptr i8, ptr %gep.1, i64 8
347 %l.5 = load float, ptr %gep.7, align 4
348 %gep.8 = getelementptr i8, ptr %gep.2, i64 8
349 %l.6 = load float, ptr %gep.8, align 4
350 %add.3 = fadd float %l.5, %l.6
351 %mul.3 = fmul float %add.3, 0.000000e+00
352 %gep.9 = getelementptr i8, ptr %gep.3, i64 8
353 store float %mul.3, ptr %gep.9, align 4
354 %i27 = getelementptr i8, ptr %gep.1, i64 12
355 %l.7 = load float, ptr %i27, align 4
356 %gep.10 = getelementptr i8, ptr %gep.2, i64 12
357 %l.8 = load float, ptr %gep.10, align 4
358 %add.4 = fadd float %l.7, %l.8
359 %mul.4 = fmul float %add.4, 0.000000e+00
360 %gep.11 = getelementptr i8, ptr %gep.3, i64 12
361 store float %mul.4, ptr %gep.11, align 4
362 %iv.next = add i64 %iv, 1
363 %ec = icmp eq i64 %iv, %arg1
364 br i1 %ec, label %exit, label %loop
366 exit:
367 ret void
368 }
370 define void @geps_feeding_interleave_groups_with_reuse2(ptr %A, ptr %B, i64 %N) #1 {
371 ; CHECK-LABEL: define void @geps_feeding_interleave_groups_with_reuse2(
372 ; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
373 ; CHECK-NEXT: [[ENTRY:.*]]:
374 ; CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[N]], 3
375 ; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[TMP0]], 1
376 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP1]], 52
377 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
378 ; CHECK: [[VECTOR_SCEVCHECK]]:
379 ; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[N]], 3
380 ; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[A]], i64 24
381 ; CHECK-NEXT: [[MUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 32, i64 [[TMP2]])
382 ; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i64, i1 } [[MUL]], 0
383 ; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i64, i1 } [[MUL]], 1
384 ; CHECK-NEXT: [[TMP3:%.*]] = sub i64 0, [[MUL_RESULT]]
385 ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[MUL_RESULT]]
386 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ult ptr [[TMP4]], [[SCEVGEP]]
387 ; CHECK-NEXT: [[TMP6:%.*]] = or i1 [[TMP5]], [[MUL_OVERFLOW]]
388 ; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[A]], i64 28
389 ; CHECK-NEXT: [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 32, i64 [[TMP2]])
390 ; CHECK-NEXT: [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
391 ; CHECK-NEXT: [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
392 ; CHECK-NEXT: [[TMP7:%.*]] = sub i64 0, [[MUL_RESULT3]]
393 ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[SCEVGEP1]], i64 [[MUL_RESULT3]]
394 ; CHECK-NEXT: [[TMP9:%.*]] = icmp ult ptr [[TMP8]], [[SCEVGEP1]]
395 ; CHECK-NEXT: [[TMP10:%.*]] = or i1 [[TMP9]], [[MUL_OVERFLOW4]]
396 ; CHECK-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[A]], i64 20
397 ; CHECK-NEXT: [[MUL6:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 32, i64 [[TMP2]])
398 ; CHECK-NEXT: [[MUL_RESULT7:%.*]] = extractvalue { i64, i1 } [[MUL6]], 0
399 ; CHECK-NEXT: [[MUL_OVERFLOW8:%.*]] = extractvalue { i64, i1 } [[MUL6]], 1
400 ; CHECK-NEXT: [[TMP11:%.*]] = sub i64 0, [[MUL_RESULT7]]
401 ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[SCEVGEP5]], i64 [[MUL_RESULT7]]
402 ; CHECK-NEXT: [[TMP13:%.*]] = icmp ult ptr [[TMP12]], [[SCEVGEP5]]
403 ; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP13]], [[MUL_OVERFLOW8]]
404 ; CHECK-NEXT: [[SCEVGEP9:%.*]] = getelementptr i8, ptr [[A]], i64 16
405 ; CHECK-NEXT: [[MUL10:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 32, i64 [[TMP2]])
406 ; CHECK-NEXT: [[MUL_RESULT11:%.*]] = extractvalue { i64, i1 } [[MUL10]], 0
407 ; CHECK-NEXT: [[MUL_OVERFLOW12:%.*]] = extractvalue { i64, i1 } [[MUL10]], 1
408 ; CHECK-NEXT: [[TMP15:%.*]] = sub i64 0, [[MUL_RESULT11]]
409 ; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[SCEVGEP9]], i64 [[MUL_RESULT11]]
410 ; CHECK-NEXT: [[TMP17:%.*]] = icmp ult ptr [[TMP16]], [[SCEVGEP9]]
411 ; CHECK-NEXT: [[TMP18:%.*]] = or i1 [[TMP17]], [[MUL_OVERFLOW12]]
412 ; CHECK-NEXT: [[SCEVGEP13:%.*]] = getelementptr i8, ptr [[A]], i64 12
413 ; CHECK-NEXT: [[MUL14:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 32, i64 [[TMP2]])
414 ; CHECK-NEXT: [[MUL_RESULT15:%.*]] = extractvalue { i64, i1 } [[MUL14]], 0
415 ; CHECK-NEXT: [[MUL_OVERFLOW16:%.*]] = extractvalue { i64, i1 } [[MUL14]], 1
416 ; CHECK-NEXT: [[TMP19:%.*]] = sub i64 0, [[MUL_RESULT15]]
417 ; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[SCEVGEP13]], i64 [[MUL_RESULT15]]
418 ; CHECK-NEXT: [[TMP21:%.*]] = icmp ult ptr [[TMP20]], [[SCEVGEP13]]
419 ; CHECK-NEXT: [[TMP22:%.*]] = or i1 [[TMP21]], [[MUL_OVERFLOW16]]
420 ; CHECK-NEXT: [[SCEVGEP17:%.*]] = getelementptr i8, ptr [[A]], i64 8
421 ; CHECK-NEXT: [[MUL18:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 32, i64 [[TMP2]])
422 ; CHECK-NEXT: [[MUL_RESULT19:%.*]] = extractvalue { i64, i1 } [[MUL18]], 0
423 ; CHECK-NEXT: [[MUL_OVERFLOW20:%.*]] = extractvalue { i64, i1 } [[MUL18]], 1
424 ; CHECK-NEXT: [[TMP23:%.*]] = sub i64 0, [[MUL_RESULT19]]
425 ; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[SCEVGEP17]], i64 [[MUL_RESULT19]]
426 ; CHECK-NEXT: [[TMP25:%.*]] = icmp ult ptr [[TMP24]], [[SCEVGEP17]]
427 ; CHECK-NEXT: [[TMP26:%.*]] = or i1 [[TMP25]], [[MUL_OVERFLOW20]]
428 ; CHECK-NEXT: [[SCEVGEP21:%.*]] = getelementptr i8, ptr [[A]], i64 4
429 ; CHECK-NEXT: [[MUL22:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 32, i64 [[TMP2]])
430 ; CHECK-NEXT: [[MUL_RESULT23:%.*]] = extractvalue { i64, i1 } [[MUL22]], 0
431 ; CHECK-NEXT: [[MUL_OVERFLOW24:%.*]] = extractvalue { i64, i1 } [[MUL22]], 1
432 ; CHECK-NEXT: [[TMP27:%.*]] = sub i64 0, [[MUL_RESULT23]]
433 ; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[SCEVGEP21]], i64 [[MUL_RESULT23]]
434 ; CHECK-NEXT: [[TMP29:%.*]] = icmp ult ptr [[TMP28]], [[SCEVGEP21]]
435 ; CHECK-NEXT: [[TMP30:%.*]] = or i1 [[TMP29]], [[MUL_OVERFLOW24]]
436 ; CHECK-NEXT: [[MUL25:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 32, i64 [[TMP2]])
437 ; CHECK-NEXT: [[MUL_RESULT26:%.*]] = extractvalue { i64, i1 } [[MUL25]], 0
438 ; CHECK-NEXT: [[MUL_OVERFLOW27:%.*]] = extractvalue { i64, i1 } [[MUL25]], 1
439 ; CHECK-NEXT: [[TMP31:%.*]] = sub i64 0, [[MUL_RESULT26]]
440 ; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[A]], i64 [[MUL_RESULT26]]
441 ; CHECK-NEXT: [[TMP33:%.*]] = icmp ult ptr [[TMP32]], [[A]]
442 ; CHECK-NEXT: [[TMP34:%.*]] = or i1 [[TMP33]], [[MUL_OVERFLOW27]]
443 ; CHECK-NEXT: [[TMP35:%.*]] = or i1 [[TMP6]], [[TMP10]]
444 ; CHECK-NEXT: [[TMP36:%.*]] = or i1 [[TMP35]], [[TMP14]]
445 ; CHECK-NEXT: [[TMP37:%.*]] = or i1 [[TMP36]], [[TMP18]]
446 ; CHECK-NEXT: [[TMP38:%.*]] = or i1 [[TMP37]], [[TMP22]]
447 ; CHECK-NEXT: [[TMP39:%.*]] = or i1 [[TMP38]], [[TMP26]]
448 ; CHECK-NEXT: [[TMP40:%.*]] = or i1 [[TMP39]], [[TMP30]]
449 ; CHECK-NEXT: [[TMP41:%.*]] = or i1 [[TMP40]], [[TMP34]]
450 ; CHECK-NEXT: br i1 [[TMP41]], label %[[SCALAR_PH]], label %[[VECTOR_MEMCHECK:.*]]
451 ; CHECK: [[VECTOR_MEMCHECK]]:
452 ; CHECK-NEXT: [[TMP42:%.*]] = lshr i64 [[N]], 3
453 ; CHECK-NEXT: [[TMP43:%.*]] = shl i64 [[TMP42]], 5
454 ; CHECK-NEXT: [[TMP44:%.*]] = add i64 [[TMP43]], 32
455 ; CHECK-NEXT: [[SCEVGEP28:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP44]]
456 ; CHECK-NEXT: [[TMP45:%.*]] = add nuw nsw i64 [[TMP43]], 4
457 ; CHECK-NEXT: [[SCEVGEP29:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP45]]
458 ; CHECK-NEXT: [[TMP46:%.*]] = shl i64 [[TMP42]], 4
459 ; CHECK-NEXT: [[TMP47:%.*]] = add nuw nsw i64 [[TMP46]], 8
460 ; CHECK-NEXT: [[SCEVGEP30:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP47]]
461 ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[A]], [[SCEVGEP29]]
462 ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[B]], [[SCEVGEP28]]
463 ; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
464 ; CHECK-NEXT: [[BOUND031:%.*]] = icmp ult ptr [[A]], [[SCEVGEP30]]
465 ; CHECK-NEXT: [[BOUND132:%.*]] = icmp ult ptr [[B]], [[SCEVGEP28]]
466 ; CHECK-NEXT: [[FOUND_CONFLICT33:%.*]] = and i1 [[BOUND031]], [[BOUND132]]
467 ; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT33]]
468 ; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
469 ; CHECK: [[VECTOR_PH]]:
470 ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 4
471 ; CHECK-NEXT: [[TMP48:%.*]] = icmp eq i64 [[N_MOD_VF]], 0
472 ; CHECK-NEXT: [[TMP49:%.*]] = select i1 [[TMP48]], i64 4, i64 [[N_MOD_VF]]
473 ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[TMP49]]
474 ; CHECK-NEXT: [[IND_END:%.*]] = mul i64 [[N_VEC]], 8
475 ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
476 ; CHECK: [[VECTOR_BODY]]:
477 ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
478 ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 8, i64 16, i64 24>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
479 ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 8
480 ; CHECK-NEXT: [[TMP50:%.*]] = add i64 [[OFFSET_IDX]], 0
481 ; CHECK-NEXT: [[TMP51:%.*]] = lshr exact i64 [[TMP50]], 1
482 ; CHECK-NEXT: [[TMP52:%.*]] = getelementptr i32, ptr [[B]], i64 [[TMP51]]
483 ; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <16 x i32>, ptr [[TMP52]], align 4
484 ; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <16 x i32> [[WIDE_VEC]], <16 x i32> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
485 ; CHECK-NEXT: [[STRIDED_VEC34:%.*]] = shufflevector <16 x i32> [[WIDE_VEC]], <16 x i32> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
486 ; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i32, ptr [[A]], i64 [[TMP50]]
487 ; CHECK-NEXT: [[TMP54:%.*]] = getelementptr i32, ptr [[B]], <4 x i64> [[VEC_IND]]
488 ; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> [[TMP54]], i32 4, <4 x i1> splat (i1 true), <4 x i32> poison), !alias.scope [[META6:![0-9]+]]
489 ; CHECK-NEXT: [[TMP58:%.*]] = shufflevector <4 x i32> [[STRIDED_VEC]], <4 x i32> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
490 ; CHECK-NEXT: [[TMP59:%.*]] = shufflevector <4 x i32> [[STRIDED_VEC34]], <4 x i32> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
491 ; CHECK-NEXT: [[TMP60:%.*]] = shufflevector <4 x i32> [[WIDE_MASKED_GATHER]], <4 x i32> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
492 ; CHECK-NEXT: [[TMP61:%.*]] = shufflevector <8 x i32> [[TMP58]], <8 x i32> [[TMP59]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
493 ; CHECK-NEXT: [[TMP62:%.*]] = shufflevector <8 x i32> [[TMP60]], <8 x i32> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
494 ; CHECK-NEXT: [[TMP63:%.*]] = shufflevector <16 x i32> [[TMP61]], <16 x i32> [[TMP62]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
495 ; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <32 x i32> [[TMP63]], <32 x i32> poison, <32 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
496 ; CHECK-NEXT: store <32 x i32> [[INTERLEAVED_VEC]], ptr [[TMP56]], align 4
497 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
498 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 32)
499 ; CHECK-NEXT: [[TMP64:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
500 ; CHECK-NEXT: br i1 [[TMP64]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
501 ; CHECK: [[MIDDLE_BLOCK]]:
502 ; CHECK-NEXT: br label %[[SCALAR_PH]]
503 ; CHECK: [[SCALAR_PH]]:
504 ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
505 ; CHECK-NEXT: br label %[[LOOP:.*]]
506 ; CHECK: [[LOOP]]:
507 ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT_7:%.*]], %[[LOOP]] ]
508 ; CHECK-NEXT: [[SHR_1:%.*]] = lshr exact i64 [[IV]], 1
509 ; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr nusw i32, ptr [[B]], i64 [[SHR_1]]
510 ; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP_B]], align 4
511 ; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr i32, ptr [[A]], i64 [[IV]]
512 ; CHECK-NEXT: store i32 [[L]], ptr [[GEP_A]], align 4
513 ; CHECK-NEXT: [[IV_NEXT:%.*]] = or disjoint i64 [[IV]], 1
514 ; CHECK-NEXT: [[GEP_A_1:%.*]] = getelementptr i32, ptr [[A]], i64 [[IV_NEXT]]
515 ; CHECK-NEXT: store i32 0, ptr [[GEP_A_1]], align 4
516 ; CHECK-NEXT: [[IV_NEXT_1:%.*]] = or disjoint i64 [[IV]], 2
517 ; CHECK-NEXT: [[SHR_2:%.*]] = lshr exact i64 [[IV_NEXT_1]], 1
518 ; CHECK-NEXT: [[GEP_B_2:%.*]] = getelementptr i32, ptr [[B]], i64 [[SHR_2]]
519 ; CHECK-NEXT: [[TMP65:%.*]] = load i32, ptr [[GEP_B_2]], align 4
520 ; CHECK-NEXT: [[GEP_A_2:%.*]] = getelementptr i32, ptr [[A]], i64 [[IV_NEXT_1]]
521 ; CHECK-NEXT: store i32 [[TMP65]], ptr [[GEP_A_2]], align 4
522 ; CHECK-NEXT: [[IV_NEXT_2:%.*]] = or disjoint i64 [[IV]], 3
523 ; CHECK-NEXT: [[GEP_A_3:%.*]] = getelementptr i32, ptr [[A]], i64 [[IV_NEXT_2]]
524 ; CHECK-NEXT: store i32 0, ptr [[GEP_A_3]], align 4
525 ; CHECK-NEXT: [[IV_NEXT_3:%.*]] = or disjoint i64 [[IV]], 4
526 ; CHECK-NEXT: [[GEP_B_4:%.*]] = getelementptr i32, ptr [[B]], i64 [[IV]]
527 ; CHECK-NEXT: [[TMP66:%.*]] = load i32, ptr [[GEP_B_4]], align 4
528 ; CHECK-NEXT: [[GEP_A_4:%.*]] = getelementptr i32, ptr [[A]], i64 [[IV_NEXT_3]]
529 ; CHECK-NEXT: store i32 [[TMP66]], ptr [[GEP_A_4]], align 4
530 ; CHECK-NEXT: [[IV_NEXT_4:%.*]] = or disjoint i64 [[IV]], 5
531 ; CHECK-NEXT: [[GEP_A_5:%.*]] = getelementptr i32, ptr [[A]], i64 [[IV_NEXT_4]]
532 ; CHECK-NEXT: store i32 0, ptr [[GEP_A_5]], align 4
533 ; CHECK-NEXT: [[IV_NEXT_5:%.*]] = or disjoint i64 [[IV]], 6
534 ; CHECK-NEXT: [[GEP_A_6:%.*]] = getelementptr i32, ptr [[A]], i64 [[IV_NEXT_5]]
535 ; CHECK-NEXT: store i32 0, ptr [[GEP_A_6]], align 4
536 ; CHECK-NEXT: [[IV_NEXT_6:%.*]] = or disjoint i64 [[IV]], 7
537 ; CHECK-NEXT: [[GEP_A_7:%.*]] = getelementptr i32, ptr [[A]], i64 [[IV_NEXT_6]]
538 ; CHECK-NEXT: store i32 0, ptr [[GEP_A_7]], align 4
539 ; CHECK-NEXT: [[IV_NEXT_7]] = add nuw nsw i64 [[IV]], 8
540 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]
541 ; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP10:![0-9]+]]
542 ; CHECK: [[EXIT]]:
543 ; CHECK-NEXT: ret void
544 ;
545 entry:
546 br label %loop
548 loop:
549 %iv = phi i64 [ 0, %entry ], [ %iv.next.7, %loop ]
550 %shr.1 = lshr exact i64 %iv, 1
551 %gep.B = getelementptr nusw i32, ptr %B, i64 %shr.1
552 %l = load i32, ptr %gep.B, align 4
553 %gep.A = getelementptr i32, ptr %A, i64 %iv
554 store i32 %l, ptr %gep.A, align 4
555 %iv.next = or disjoint i64 %iv, 1
556 %gep.A.1 = getelementptr i32, ptr %A, i64 %iv.next
557 store i32 0, ptr %gep.A.1, align 4
558 %iv.next.1 = or disjoint i64 %iv, 2
559 %shr.2 = lshr exact i64 %iv.next.1, 1
560 %gep.B.2 = getelementptr i32, ptr %B, i64 %shr.2
561 %1 = load i32, ptr %gep.B.2, align 4
562 %gep.A.2 = getelementptr i32, ptr %A, i64 %iv.next.1
563 store i32 %1, ptr %gep.A.2, align 4
564 %iv.next.2 = or disjoint i64 %iv, 3
565 %gep.A.3 = getelementptr i32, ptr %A, i64 %iv.next.2
566 store i32 0, ptr %gep.A.3, align 4
567 %iv.next.3 = or disjoint i64 %iv, 4
568 %gep.B.4 = getelementptr i32, ptr %B, i64 %iv
569 %2 = load i32, ptr %gep.B.4, align 4
570 %gep.A.4 = getelementptr i32, ptr %A, i64 %iv.next.3
571 store i32 %2, ptr %gep.A.4, align 4
572 %iv.next.4 = or disjoint i64 %iv, 5
573 %gep.A.5 = getelementptr i32, ptr %A, i64 %iv.next.4
574 store i32 0, ptr %gep.A.5, align 4
575 %iv.next.5 = or disjoint i64 %iv, 6
576 %gep.A.6 = getelementptr i32, ptr %A, i64 %iv.next.5
577 store i32 0, ptr %gep.A.6, align 4
578 %iv.next.6 = or disjoint i64 %iv, 7
579 %gep.A.7 = getelementptr i32, ptr %A, i64 %iv.next.6
580 store i32 0, ptr %gep.A.7, align 4
581 %iv.next.7 = add nuw nsw i64 %iv, 8
582 %ec = icmp eq i64 %iv, %N
583 br i1 %ec, label %exit, label %loop
585 exit:
586 ret void
587 }
589 ; Test case for https://github.com/llvm/llvm-project/issues/112922.
590 define void @interleave_store_double_i64(ptr %dst) {
591 ; CHECK-LABEL: define void @interleave_store_double_i64(
592 ; CHECK-SAME: ptr [[DST:%.*]]) {
593 ; CHECK-NEXT: [[ENTRY:.*]]:
594 ; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
595 ; CHECK: [[VECTOR_PH]]:
596 ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
597 ; CHECK: [[VECTOR_BODY]]:
598 ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
599 ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
600 ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
601 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr { double, i64 }, ptr [[DST]], i64 [[TMP0]]
602 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[VEC_IND]] to <2 x double>
603 ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> zeroinitializer, <2 x double> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
604 ; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x double> [[TMP3]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
605 ; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP1]], align 8
606 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], splat (i64 2)
607 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
608 ; CHECK-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
609 ; CHECK: [[MIDDLE_BLOCK]]:
610 ; CHECK-NEXT: br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]]
611 ; CHECK: [[SCALAR_PH]]:
612 ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 2, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
613 ; CHECK-NEXT: br label %[[LOOP:.*]]
614 ; CHECK: [[LOOP]]:
615 ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
616 ; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr { double, i64 }, ptr [[DST]], i64 [[IV]], i32 1
617 ; CHECK-NEXT: store i64 [[IV]], ptr [[GEP_1]], align 8
618 ; CHECK-NEXT: [[GEP_0:%.*]] = getelementptr { double, i64 }, ptr [[DST]], i64 [[IV]]
619 ; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_0]], align 8
620 ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
621 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 1
622 ; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP12:![0-9]+]]
623 ; CHECK: [[EXIT]]:
624 ; CHECK-NEXT: ret void
625 ;
626 entry:
627 br label %loop
629 loop:
630 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
631 %gep.1 = getelementptr { double, i64 }, ptr %dst, i64 %iv, i32 1
632 store i64 %iv, ptr %gep.1, align 8
633 %gep.0 = getelementptr { double, i64 }, ptr %dst, i64 %iv
634 store double 0.000000e+00, ptr %gep.0, align 8
635 %iv.next = add i64 %iv, 1
636 %ec = icmp eq i64 %iv, 1
637 br i1 %ec, label %exit, label %loop
639 exit:
640 ret void
641 }
643 define void @interleave_store_i64_double(ptr %dst) {
644 ; CHECK-LABEL: define void @interleave_store_i64_double(
645 ; CHECK-SAME: ptr [[DST:%.*]]) {
646 ; CHECK-NEXT: [[ENTRY:.*]]:
647 ; CHECK-NEXT: br label %[[LOOP:.*]]
648 ; CHECK: [[LOOP]]:
649 ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
650 ; CHECK-NEXT: [[GEP_0:%.*]] = getelementptr { double, i64 }, ptr [[DST]], i64 [[IV]]
651 ; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_0]], align 8
652 ; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr { double, i64 }, ptr [[DST]], i64 [[IV]], i32 1
653 ; CHECK-NEXT: store i64 [[IV]], ptr [[GEP_1]], align 8
654 ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
655 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 1
656 ; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]
657 ; CHECK: [[EXIT]]:
658 ; CHECK-NEXT: ret void
659 ;
660 entry:
661 br label %loop
663 loop:
664 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
665 %gep.0 = getelementptr { double, i64 }, ptr %dst, i64 %iv
666 store double 0.000000e+00, ptr %gep.0, align 8
667 %gep.1 = getelementptr { double, i64 }, ptr %dst, i64 %iv, i32 1
668 store i64 %iv, ptr %gep.1, align 8
669 %iv.next = add i64 %iv, 1
670 %ec = icmp eq i64 %iv, 1
671 br i1 %ec, label %exit, label %loop
673 exit:
674 ret void
675 }
677 ; TODO: The interleave group should likely have the same cost as @interleave_store_double_i64.
678 define void @interleave_store_double_i64_2(ptr %dst) {
679 ; CHECK-LABEL: define void @interleave_store_double_i64_2(
680 ; CHECK-SAME: ptr [[DST:%.*]]) {
681 ; CHECK-NEXT: [[ENTRY:.*]]:
682 ; CHECK-NEXT: br label %[[LOOP:.*]]
683 ; CHECK: [[LOOP]]:
684 ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
685 ; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr { i64, double }, ptr [[DST]], i64 [[IV]], i32 1
686 ; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_1]], align 8
687 ; CHECK-NEXT: [[GEP_0:%.*]] = getelementptr { i64, double }, ptr [[DST]], i64 [[IV]]
688 ; CHECK-NEXT: store i64 [[IV]], ptr [[GEP_0]], align 8
689 ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
690 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 1
691 ; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]
692 ; CHECK: [[EXIT]]:
693 ; CHECK-NEXT: ret void
694 ;
695 entry:
696 br label %loop
698 loop:
699 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
700 %gep.1 = getelementptr { i64, double }, ptr %dst, i64 %iv, i32 1
701 store double 0.000000e+00, ptr %gep.1, align 8
702 %gep.0 = getelementptr { i64, double }, ptr %dst, i64 %iv
703 store i64 %iv, ptr %gep.0, align 8
704 %iv.next = add i64 %iv, 1
705 %ec = icmp eq i64 %iv, 1
706 br i1 %ec, label %exit, label %loop
708 exit:
709 ret void
710 }
712 define void @interleave_store_i64_double_2(ptr %dst) {
713 ; CHECK-LABEL: define void @interleave_store_i64_double_2(
714 ; CHECK-SAME: ptr [[DST:%.*]]) {
715 ; CHECK-NEXT: [[ENTRY:.*]]:
716 ; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
717 ; CHECK: [[VECTOR_PH]]:
718 ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
719 ; CHECK: [[VECTOR_BODY]]:
720 ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
721 ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
722 ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
723 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr { i64, double }, ptr [[DST]], i64 [[TMP0]]
724 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[VEC_IND]] to <2 x double>
725 ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
726 ; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x double> [[TMP3]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
727 ; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP1]], align 8
728 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], splat (i64 2)
729 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
730 ; CHECK-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
731 ; CHECK: [[MIDDLE_BLOCK]]:
732 ; CHECK-NEXT: br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]]
733 ; CHECK: [[SCALAR_PH]]:
734 ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 2, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
735 ; CHECK-NEXT: br label %[[LOOP:.*]]
736 ; CHECK: [[LOOP]]:
737 ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
738 ; CHECK-NEXT: [[GEP_0:%.*]] = getelementptr { i64, double }, ptr [[DST]], i64 [[IV]]
739 ; CHECK-NEXT: store i64 [[IV]], ptr [[GEP_0]], align 8
740 ; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr { i64, double }, ptr [[DST]], i64 [[IV]], i32 1
741 ; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_1]], align 8
742 ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
743 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 1
744 ; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP14:![0-9]+]]
745 ; CHECK: [[EXIT]]:
746 ; CHECK-NEXT: ret void
747 ;
748 entry:
749 br label %loop
751 loop:
752 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
753 %gep.0 = getelementptr { i64, double }, ptr %dst, i64 %iv
754 store i64 %iv, ptr %gep.0, align 8
755 %gep.1 = getelementptr { i64, double }, ptr %dst, i64 %iv, i32 1
756 store double 0.000000e+00, ptr %gep.1, align 8
757 %iv.next = add i64 %iv, 1
758 %ec = icmp eq i64 %iv, 1
759 br i1 %ec, label %exit, label %loop
761 exit:
762 ret void
763 }
767 attributes #0 = { "target-features"="+sse4.2" }
768 attributes #1 = { "min-legal-vector-width"="0" "target-cpu"="cascadelake" }
770 ;.
771 ; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
772 ; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
773 ; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
774 ; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
775 ; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
776 ; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
777 ; CHECK: [[META6]] = !{[[META7:![0-9]+]]}
778 ; CHECK: [[META7]] = distinct !{[[META7]], [[META8:![0-9]+]]}
779 ; CHECK: [[META8]] = distinct !{[[META8]], !"LVerDomain"}
780 ; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]], [[META2]]}
781 ; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]]}
782 ; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]], [[META2]]}
783 ; CHECK: [[LOOP12]] = distinct !{[[LOOP12]], [[META2]], [[META1]]}
784 ; CHECK: [[LOOP13]] = distinct !{[[LOOP13]], [[META1]], [[META2]]}
785 ; CHECK: [[LOOP14]] = distinct !{[[LOOP14]], [[META2]], [[META1]]}
786 ;.