1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt -passes=loop-vectorize -force-vector-width=2 %s -S | FileCheck %s
4 ; Test case for PR47343. Make sure LCSSA phis are create correctly when
5 ; expanding the memory runtime checks.
7 @f.e = external global i32, align 1
8 @d = external global ptr, align 1
15 ; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]
16 ; CHECK: outer.header:
17 ; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr @d, align 1
18 ; CHECK-NEXT: [[C_0:%.*]] = call i1 @cond()
19 ; CHECK-NEXT: br i1 [[C_0]], label [[OUTER_EXIT_0:%.*]], label [[INNER_1_HEADER_PREHEADER:%.*]]
20 ; CHECK: inner.1.header.preheader:
21 ; CHECK-NEXT: br label [[INNER_1_HEADER:%.*]]
22 ; CHECK: inner.1.header:
23 ; CHECK-NEXT: [[C_1:%.*]] = call i1 @cond()
24 ; CHECK-NEXT: br i1 [[C_1]], label [[INNER_1_LATCH:%.*]], label [[OUTER_LATCH:%.*]]
25 ; CHECK: inner.1.latch:
26 ; CHECK-NEXT: [[C_2:%.*]] = call i1 @cond()
27 ; CHECK-NEXT: br i1 [[C_2]], label [[OUTER_EXIT_1:%.*]], label [[INNER_1_HEADER]]
29 ; CHECK-NEXT: br label [[OUTER_HEADER]]
30 ; CHECK: outer.exit.0:
31 ; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi ptr [ [[TMP0]], [[OUTER_HEADER]] ]
32 ; CHECK-NEXT: br label [[LOOP_PREHEADER:%.*]]
33 ; CHECK: outer.exit.1:
34 ; CHECK-NEXT: [[DOTLCSSA1:%.*]] = phi ptr [ [[TMP0]], [[INNER_1_LATCH]] ]
35 ; CHECK-NEXT: br label [[LOOP_PREHEADER]]
36 ; CHECK: loop.preheader:
37 ; CHECK-NEXT: [[TMP1:%.*]] = phi ptr [ [[DOTLCSSA]], [[OUTER_EXIT_0]] ], [ [[DOTLCSSA1]], [[OUTER_EXIT_1]] ]
38 ; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]]
39 ; CHECK: vector.memcheck:
40 ; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[TMP1]], i64 1
41 ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr @f.e, [[SCEVGEP]]
42 ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[TMP1]], getelementptr inbounds nuw (i8, ptr @f.e, i64 4)
43 ; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
44 ; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
46 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
48 ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
49 ; CHECK-NEXT: store i32 0, ptr @f.e, align 1, !alias.scope [[META0:![0-9]+]], !noalias [[META3:![0-9]+]]
50 ; CHECK-NEXT: store i8 10, ptr [[TMP0]], align 1
51 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
52 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[INDEX_NEXT]], 500
53 ; CHECK-NEXT: br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
54 ; CHECK: middle.block:
55 ; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]]
57 ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 500, [[MIDDLE_BLOCK]] ], [ 0, [[LOOP_PREHEADER]] ], [ 0, [[VECTOR_MEMCHECK]] ]
58 ; CHECK-NEXT: br label [[LOOP:%.*]]
60 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
61 ; CHECK-NEXT: [[CONV6_US_US_US:%.*]] = zext i1 false to i32
62 ; CHECK-NEXT: store i32 [[CONV6_US_US_US]], ptr @f.e, align 1
63 ; CHECK-NEXT: store i8 10, ptr [[TMP1]], align 1
64 ; CHECK-NEXT: [[IV_NEXT]] = add nsw i32 [[IV]], 1
65 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], 500
66 ; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP8:![0-9]+]]
68 ; CHECK-NEXT: ret void
71 br label %outer.header
73 outer.header: ; preds = %cleanup, %entry
74 %0 = load ptr, ptr @d, align 1
75 %c.0 = call i1 @cond()
76 br i1 %c.0, label %outer.exit.0, label %inner.1.header
78 inner.1.header: ; preds = %if.end, %for.body3.lr.ph.outer
79 %c.1 = call i1 @cond()
80 br i1 %c.1, label %inner.1.latch, label %outer.latch
82 inner.1.latch: ; preds = %land.end
83 %c.2 = call i1 @cond()
84 br i1 %c.2, label %outer.exit.1, label %inner.1.header
86 outer.latch: ; preds = %land.end
87 br label %outer.header
90 outer.exit.0: ; preds = %if.end, %if.end.us.us.us
93 outer.exit.1: ; preds = %if.end, %if.end.us.us.us
96 loop: ; preds = %if.end.us.us.us, %for.body3.lr.ph.outer
97 %iv = phi i32 [ %iv.next, %loop ], [ 0, %outer.exit.0 ], [ 0, %outer.exit.1 ]
98 %conv6.us.us.us = zext i1 false to i32
99 store i32 %conv6.us.us.us, ptr @f.e, align 1
100 store i8 10, ptr %0, align 1
101 %iv.next = add nsw i32 %iv, 1
102 %ec = icmp eq i32 %iv.next, 500
103 br i1 %ec, label %exit, label %loop