| blob | 10f07f158175d06704132e9dff721d223ad0aa2f |
1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=aarch64-unknown-unknown -mcpu=cortex-a53 | FileCheck %s
4 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
6 ; This test is reduced from the matrix multiplication benchmark in the test-suite:
7 ; https://github.com/llvm/llvm-test-suite/tree/main/SingleSource/Benchmarks/Misc/matmul_f64_4x4.c
8 ; The operations here are expected to be vectorized to <2 x double>.
9 ; Otherwise, performance will suffer on Cortex-A53.
11 define void @wrap_mul4(ptr nocapture %Out, ptr nocapture readonly %A, ptr nocapture readonly %B) {
12 ; CHECK-LABEL: @wrap_mul4(
13 ; CHECK-NEXT: [[TEMP:%.*]] = load double, ptr [[A:%.*]], align 8
14 ; CHECK-NEXT: [[ARRAYIDX5_I:%.*]] = getelementptr inbounds [2 x double], ptr [[A]], i64 0, i64 1
15 ; CHECK-NEXT: [[TEMP2:%.*]] = load double, ptr [[ARRAYIDX5_I]], align 8
16 ; CHECK-NEXT: [[ARRAYIDX7_I:%.*]] = getelementptr inbounds [4 x double], ptr [[B:%.*]], i64 1, i64 0
17 ; CHECK-NEXT: [[ARRAYIDX25_I:%.*]] = getelementptr inbounds [4 x double], ptr [[B]], i64 0, i64 2
18 ; CHECK-NEXT: [[ARRAYIDX30_I:%.*]] = getelementptr inbounds [4 x double], ptr [[B]], i64 1, i64 2
19 ; CHECK-NEXT: [[ARRAYIDX47_I:%.*]] = getelementptr inbounds [2 x double], ptr [[A]], i64 1, i64 0
20 ; CHECK-NEXT: [[TEMP10:%.*]] = load double, ptr [[ARRAYIDX47_I]], align 8
21 ; CHECK-NEXT: [[ARRAYIDX52_I:%.*]] = getelementptr inbounds [2 x double], ptr [[A]], i64 1, i64 1
22 ; CHECK-NEXT: [[TEMP11:%.*]] = load double, ptr [[ARRAYIDX52_I]], align 8
23 ; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[B]], align 8
24 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[TEMP]], i32 0
25 ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
26 ; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[TMP3]], [[TMP1]]
27 ; CHECK-NEXT: [[TMP5:%.*]] = load <2 x double>, ptr [[ARRAYIDX7_I]], align 8
28 ; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x double> poison, double [[TEMP2]], i32 0
29 ; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x double> [[TMP6]], <2 x double> poison, <2 x i32> zeroinitializer
30 ; CHECK-NEXT: [[TMP8:%.*]] = fmul <2 x double> [[TMP7]], [[TMP5]]
31 ; CHECK-NEXT: [[TMP9:%.*]] = fadd <2 x double> [[TMP4]], [[TMP8]]
32 ; CHECK-NEXT: [[RES_I_SROA_5_0_OUT2_I_SROA_IDX4:%.*]] = getelementptr inbounds double, ptr [[OUT:%.*]], i64 2
33 ; CHECK-NEXT: [[TMP10:%.*]] = load <2 x double>, ptr [[ARRAYIDX25_I]], align 8
34 ; CHECK-NEXT: [[TMP11:%.*]] = fmul <2 x double> [[TMP3]], [[TMP10]]
35 ; CHECK-NEXT: [[TMP12:%.*]] = load <2 x double>, ptr [[ARRAYIDX30_I]], align 8
36 ; CHECK-NEXT: [[TMP13:%.*]] = fmul <2 x double> [[TMP7]], [[TMP12]]
37 ; CHECK-NEXT: [[TMP14:%.*]] = fadd <2 x double> [[TMP11]], [[TMP13]]
38 ; CHECK-NEXT: store <2 x double> [[TMP9]], ptr [[OUT]], align 8
39 ; CHECK-NEXT: store <2 x double> [[TMP14]], ptr [[RES_I_SROA_5_0_OUT2_I_SROA_IDX4]], align 8
40 ; CHECK-NEXT: [[RES_I_SROA_7_0_OUT2_I_SROA_IDX8:%.*]] = getelementptr inbounds double, ptr [[OUT]], i64 4
41 ; CHECK-NEXT: [[TMP15:%.*]] = insertelement <2 x double> poison, double [[TEMP10]], i32 0
42 ; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <2 x double> [[TMP15]], <2 x double> poison, <2 x i32> zeroinitializer
43 ; CHECK-NEXT: [[TMP17:%.*]] = fmul <2 x double> [[TMP1]], [[TMP16]]
44 ; CHECK-NEXT: [[TMP18:%.*]] = insertelement <2 x double> poison, double [[TEMP11]], i32 0
45 ; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <2 x double> [[TMP18]], <2 x double> poison, <2 x i32> zeroinitializer
46 ; CHECK-NEXT: [[TMP20:%.*]] = fmul <2 x double> [[TMP5]], [[TMP19]]
47 ; CHECK-NEXT: [[TMP21:%.*]] = fadd <2 x double> [[TMP17]], [[TMP20]]
48 ; CHECK-NEXT: store <2 x double> [[TMP21]], ptr [[RES_I_SROA_7_0_OUT2_I_SROA_IDX8]], align 8
49 ; CHECK-NEXT: [[RES_I_SROA_9_0_OUT2_I_SROA_IDX12:%.*]] = getelementptr inbounds double, ptr [[OUT]], i64 6
50 ; CHECK-NEXT: [[TMP22:%.*]] = fmul <2 x double> [[TMP10]], [[TMP16]]
51 ; CHECK-NEXT: [[TMP23:%.*]] = fmul <2 x double> [[TMP12]], [[TMP19]]
52 ; CHECK-NEXT: [[TMP24:%.*]] = fadd <2 x double> [[TMP22]], [[TMP23]]
53 ; CHECK-NEXT: store <2 x double> [[TMP24]], ptr [[RES_I_SROA_9_0_OUT2_I_SROA_IDX12]], align 8
54 ; CHECK-NEXT: ret void
55 ;
56 %temp = load double, ptr %A, align 8
57 %temp1 = load double, ptr %B, align 8
58 %mul.i = fmul double %temp, %temp1
59 %arrayidx5.i = getelementptr inbounds [2 x double], ptr %A, i64 0, i64 1
60 %temp2 = load double, ptr %arrayidx5.i, align 8
61 %arrayidx7.i = getelementptr inbounds [4 x double], ptr %B, i64 1, i64 0
62 %temp3 = load double, ptr %arrayidx7.i, align 8
63 %mul8.i = fmul double %temp2, %temp3
64 %add.i = fadd double %mul.i, %mul8.i
65 %arrayidx13.i = getelementptr inbounds [4 x double], ptr %B, i64 0, i64 1
66 %temp4 = load double, ptr %arrayidx13.i, align 8
67 %mul14.i = fmul double %temp, %temp4
68 %arrayidx18.i = getelementptr inbounds [4 x double], ptr %B, i64 1, i64 1
69 %temp5 = load double, ptr %arrayidx18.i, align 8
70 %mul19.i = fmul double %temp2, %temp5
71 %add20.i = fadd double %mul14.i, %mul19.i
72 %arrayidx25.i = getelementptr inbounds [4 x double], ptr %B, i64 0, i64 2
73 %temp6 = load double, ptr %arrayidx25.i, align 8
74 %mul26.i = fmul double %temp, %temp6
75 %arrayidx30.i = getelementptr inbounds [4 x double], ptr %B, i64 1, i64 2
76 %temp7 = load double, ptr %arrayidx30.i, align 8
77 %mul31.i = fmul double %temp2, %temp7
78 %add32.i = fadd double %mul26.i, %mul31.i
79 %arrayidx37.i = getelementptr inbounds [4 x double], ptr %B, i64 0, i64 3
80 %temp8 = load double, ptr %arrayidx37.i, align 8
81 %mul38.i = fmul double %temp, %temp8
82 %arrayidx42.i = getelementptr inbounds [4 x double], ptr %B, i64 1, i64 3
83 %temp9 = load double, ptr %arrayidx42.i, align 8
84 %mul43.i = fmul double %temp2, %temp9
85 %add44.i = fadd double %mul38.i, %mul43.i
86 %arrayidx47.i = getelementptr inbounds [2 x double], ptr %A, i64 1, i64 0
87 %temp10 = load double, ptr %arrayidx47.i, align 8
88 %mul50.i = fmul double %temp1, %temp10
89 %arrayidx52.i = getelementptr inbounds [2 x double], ptr %A, i64 1, i64 1
90 %temp11 = load double, ptr %arrayidx52.i, align 8
91 %mul55.i = fmul double %temp3, %temp11
92 %add56.i = fadd double %mul50.i, %mul55.i
93 %mul62.i = fmul double %temp4, %temp10
94 %mul67.i = fmul double %temp5, %temp11
95 %add68.i = fadd double %mul62.i, %mul67.i
96 %mul74.i = fmul double %temp6, %temp10
97 %mul79.i = fmul double %temp7, %temp11
98 %add80.i = fadd double %mul74.i, %mul79.i
99 %mul86.i = fmul double %temp8, %temp10
100 %mul91.i = fmul double %temp9, %temp11
101 %add92.i = fadd double %mul86.i, %mul91.i
102 store double %add.i, ptr %Out, align 8
103 %Res.i.sroa.4.0.Out2.i.sroa_idx2 = getelementptr inbounds double, ptr %Out, i64 1
104 store double %add20.i, ptr %Res.i.sroa.4.0.Out2.i.sroa_idx2, align 8
105 %Res.i.sroa.5.0.Out2.i.sroa_idx4 = getelementptr inbounds double, ptr %Out, i64 2
106 store double %add32.i, ptr %Res.i.sroa.5.0.Out2.i.sroa_idx4, align 8
107 %Res.i.sroa.6.0.Out2.i.sroa_idx6 = getelementptr inbounds double, ptr %Out, i64 3
108 store double %add44.i, ptr %Res.i.sroa.6.0.Out2.i.sroa_idx6, align 8
109 %Res.i.sroa.7.0.Out2.i.sroa_idx8 = getelementptr inbounds double, ptr %Out, i64 4
110 store double %add56.i, ptr %Res.i.sroa.7.0.Out2.i.sroa_idx8, align 8
111 %Res.i.sroa.8.0.Out2.i.sroa_idx10 = getelementptr inbounds double, ptr %Out, i64 5
112 store double %add68.i, ptr %Res.i.sroa.8.0.Out2.i.sroa_idx10, align 8
113 %Res.i.sroa.9.0.Out2.i.sroa_idx12 = getelementptr inbounds double, ptr %Out, i64 6
114 store double %add80.i, ptr %Res.i.sroa.9.0.Out2.i.sroa_idx12, align 8
115 %Res.i.sroa.10.0.Out2.i.sroa_idx14 = getelementptr inbounds double, ptr %Out, i64 7
116 store double %add92.i, ptr %Res.i.sroa.10.0.Out2.i.sroa_idx14, align 8
117 ret void
118 }