| blob | 1e3e8856df3d107352ac30d19e69c6a842f5666e |
1 ; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s
3 ; --------------------------------------------------------------------
4 ; Wrong mangled types
5 ; --------------------------------------------------------------------
7 ; CHECK: operand 0 must be 4, 6 or 8 element i32 vector
8 ; CHECK-NEXT: %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v4i64.v8i32(<4 x i64> %arg0, <8 x i32> %arg1, <4 x float> %arg2, i32 0, i32 2, i32 0, i32 %scale0, i32 0, i32 %scale1)
9 ; CHECK-NEXT: <4 x i64> %arg0
10 define <4 x float> @test_mfma_scale_f32_16x16x128_f8f6f4___v4i64_fp8__v8i32_fp8(<4 x i64> %arg0, <8 x i32> %arg1, <4 x float> %arg2, i32 %scale0, i32 %scale1) {
11 %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v4i64.v8i32(<4 x i64> %arg0, <8 x i32> %arg1, <4 x float> %arg2,
12 i32 0, ; cbsz
13 i32 2, ; blgp
14 i32 0, i32 %scale0, i32 0, i32 %scale1)
15 ret <4 x float> %result
16 }
18 ; CHECK: operand 1 must be 4, 6 or 8 element i32 vector
19 ; CHECK-NEXT: %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v8i32.v4i64(<8 x i32> %arg0, <4 x i64> %arg1, <4 x float> %arg2, i32 0, i32 2, i32 0, i32 %scale0, i32 0, i32 %scale1)
20 ; CHECK-NEXT: <4 x i64> %arg1
21 define <4 x float> @test_mfma_scale_f32_16x16x128_f8f6f4___v8i32_fp8v4i64_fp8(<8 x i32> %arg0, <4 x i64> %arg1, <4 x float> %arg2, i32 %scale0, i32 %scale1) {
22 %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v8i32.v4i64(<8 x i32> %arg0, <4 x i64> %arg1, <4 x float> %arg2,
23 i32 0, ; cbsz
24 i32 2, ; blgp
25 i32 0, i32 %scale0, i32 0, i32 %scale1)
26 ret <4 x float> %result
27 }
29 ; CHECK: operand 0 must be 4, 6 or 8 element i32 vector
30 ; CHECK: %result = call <16 x float> @llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.v4i64.v8i32(<4 x i64> %arg0, <8 x i32> %arg1, <16 x float> %arg2, i32 0, i32 2, i32 0, i32 %scale0, i32 0, i32 %scale1)
31 ; CHECK: <4 x i64> %arg0
32 define <16 x float> @test_mfma_scale_f32_32x32x64_f8f6f4___v4i64_fp8__v8i32_fp8(<4 x i64> %arg0, <8 x i32> %arg1, <16 x float> %arg2, i32 %scale0, i32 %scale1) {
33 %result = call <16 x float> @llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.v4i64.v8i32(<4 x i64> %arg0, <8 x i32> %arg1, <16 x float> %arg2,
34 i32 0, ; cbsz
35 i32 2, ; blgp
36 i32 0, i32 %scale0, i32 0, i32 %scale1)
37 ret <16 x float> %result
38 }
40 ; CHECK: operand 1 must be 4, 6 or 8 element i32 vector
41 ; CHECK-NEXT: %result = call <16 x float> @llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.v8i32.v4i64(<8 x i32> %arg0, <4 x i64> %arg1, <16 x float> %arg2, i32 0, i32 2, i32 0, i32 %scale0, i32 0, i32 %scale1)
42 ; CHECK-NEXT: <4 x i64> %arg1
43 define <16 x float> @test_mfma_scale_f32_32x32x64_f8f6f4___v8i32_fp8v4i64_fp8(<8 x i32> %arg0, <4 x i64> %arg1, <16 x float> %arg2, i32 %scale0, i32 %scale1) {
44 %result = call <16 x float> @llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.v8i32.v4i64(<8 x i32> %arg0, <4 x i64> %arg1, <16 x float> %arg2,
45 i32 0, ; cbsz
46 i32 2, ; blgp
47 i32 0, i32 %scale0, i32 0, i32 %scale1)
48 ret <16 x float> %result
49 }
51 ; --------------------------------------------------------------------
52 ; Impossible vector types
53 ; --------------------------------------------------------------------
55 ; CHECK: operand 0 must be 4, 6 or 8 element i32 vector
56 ; CHECK-NEXT: %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v5i32.v8i32(<5 x i32> %arg0, <8 x i32> %arg1, <4 x float> %arg2, i32 4, i32 4, i32 0, i32 %scale0, i32 0, i32 %scale1)
57 ; CHECK-NEXT: <5 x i32> %arg0
58 define <4 x float> @test_mfma_scale_f32_16x16x128_f8f6f4___v5i32_fp4__v8i32_fp4(<5 x i32> %arg0, <8 x i32> %arg1, <4 x float> %arg2, i32 %scale0, i32 %scale1) {
59 %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v4i64.v8i32(<5 x i32> %arg0, <8 x i32> %arg1, <4 x float> %arg2,
60 i32 4, ; cbsz
61 i32 4, ; blgp
62 i32 0, i32 %scale0, i32 0, i32 %scale1)
63 ret <4 x float> %result
64 }
66 ; CHECK: operand 1 must be 4, 6 or 8 element i32 vector
67 ; CHECK-NEXT: %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v8i32.v5i32(<8 x i32> %arg0, <5 x i32> %arg1, <4 x float> %arg2, i32 4, i32 4, i32 0, i32 %scale0, i32 0, i32 %scale1)
68 ; CHECK-NEXT: <5 x i32> %arg1
69 define <4 x float> @test_mfma_scale_f32_16x16x128_f8f6f4___v8i32_fp4__v5i32_fp4(<8 x i32> %arg0, <5 x i32> %arg1, <4 x float> %arg2, i32 %scale0, i32 %scale1) {
70 %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v8i32.v5i32(<8 x i32> %arg0, <5 x i32> %arg1, <4 x float> %arg2,
71 i32 4, ; cbsz
72 i32 4, ; blgp
73 i32 0, i32 %scale0, i32 0, i32 %scale1)
74 ret <4 x float> %result
75 }
77 ; CHECK: operand 0 must be 4, 6 or 8 element i32 vector
78 ; CHECK-NEXT: %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v7i32.v8i32(<7 x i32> %arg0, <8 x i32> %arg1, <4 x float> %arg2, i32 4, i32 4, i32 0, i32 %scale0, i32 0, i32 %scale1)
79 ; CHECK-NEXT: <7 x i32> %arg0
80 define <4 x float> @test_mfma_scale_f32_16x16x128_f8f6f4___v7i32_fp4__v8i32_fp4(<7 x i32> %arg0, <8 x i32> %arg1, <4 x float> %arg2, i32 %scale0, i32 %scale1) {
81 %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v4i64.v8i32(<7 x i32> %arg0, <8 x i32> %arg1, <4 x float> %arg2,
82 i32 4, ; cbsz
83 i32 4, ; blgp
84 i32 0, i32 %scale0, i32 0, i32 %scale1)
85 ret <4 x float> %result
86 }
88 ; CHECK: operand 1 must be 4, 6 or 8 element i32 vector
89 ; CHECK-NEXT: %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v8i32.v7i32(<8 x i32> %arg0, <7 x i32> %arg1, <4 x float> %arg2, i32 4, i32 4, i32 0, i32 %scale0, i32 0, i32 %scale1)
90 ; CHECK-NEXT: <7 x i32> %arg1
91 define <4 x float> @test_mfma_scale_f32_16x16x128_f8f6f4___v8i32_fp4__v7i32_fp4(<8 x i32> %arg0, <7 x i32> %arg1, <4 x float> %arg2, i32 %scale0, i32 %scale1) {
92 %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v8i32.v7i32(<8 x i32> %arg0, <7 x i32> %arg1, <4 x float> %arg2,
93 i32 4, ; cbsz
94 i32 4, ; blgp
95 i32 0, i32 %scale0, i32 0, i32 %scale1)
96 ret <4 x float> %result
97 }
99 ; --------------------------------------------------------------------
100 ; Out of bounds format
101 ; --------------------------------------------------------------------
103 ; CHECK: invalid value for cbsz format
104 ; CHECK-NEXT: %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v8i32.v8i32(<8 x i32> %arg0, <8 x i32> %arg1, <4 x float> %arg2, i32 9999, i32 2, i32 0, i32 %scale0, i32 0, i32 %scale1)
105 ; CHECK-NEXT: i32 9999
106 define <4 x float> @test_mfma_scale_f32_16x16x128_f8f6f4___v8i32_invalid0__v8i32_fp6(<8 x i32> %arg0, <8 x i32> %arg1, <4 x float> %arg2, i32 %scale0, i32 %scale1) {
107 %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v8i32.v8i32(<8 x i32> %arg0, <8 x i32> %arg1, <4 x float> %arg2,
108 i32 9999, ; cbsz
109 i32 2, ; blgp
110 i32 0, i32 %scale0, i32 0, i32 %scale1)
111 ret <4 x float> %result
112 }
114 ; CHECK: invalid value for blgp format
115 ; CHECK-NEXT: %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v8i32.v8i32(<8 x i32> %arg0, <8 x i32> %arg1, <4 x float> %arg2, i32 0, i32 9999, i32 0, i32 %scale0, i32 0, i32 %scale1)
116 ; CHECK-NEXT: i32 9999
117 define <4 x float> @test_mfma_scale_f32_16x16x128_f8f6f4___v8i32_fp8__v8i32_invalid0(<8 x i32> %arg0, <8 x i32> %arg1, <4 x float> %arg2, i32 %scale0, i32 %scale1) {
118 %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v8i32.v8i32(<8 x i32> %arg0, <8 x i32> %arg1, <4 x float> %arg2,
119 i32 0, ; cbsz
120 i32 9999, ; blgp
121 i32 0, i32 %scale0, i32 0, i32 %scale1)
122 ret <4 x float> %result
123 }
125 ; CHECK: invalid value for cbsz format
126 ; CHECK-NEXT: %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v8i32.v8i32(<8 x i32> %arg0, <8 x i32> %arg1, <4 x float> %arg2, i32 5, i32 2, i32 0, i32 %scale0, i32 0, i32 %scale1)
127 ; CHECK-NEXT: i32 5
128 define <4 x float> @test_mfma_scale_f32_16x16x128_f8f6f4___v8i32_invalid1__v8i32_fp6(<8 x i32> %arg0, <8 x i32> %arg1, <4 x float> %arg2, i32 %scale0, i32 %scale1) {
129 %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v8i32.v8i32(<8 x i32> %arg0, <8 x i32> %arg1, <4 x float> %arg2,
130 i32 5, ; cbsz
131 i32 2, ; blgp
132 i32 0, i32 %scale0, i32 0, i32 %scale1)
133 ret <4 x float> %result
134 }
136 ; CHECK: invalid value for blgp format
137 ; CHECK-NEXT: %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v8i32.v8i32(<8 x i32> %arg0, <8 x i32> %arg1, <4 x float> %arg2, i32 0, i32 5, i32 0, i32 %scale0, i32 0, i32 %scale1)
138 ; CHECK-NEXT: i32 5
139 define <4 x float> @test_mfma_scale_f32_16x16x128_f8f6f4___v8i32_fp8__v8i321_invalid(<8 x i32> %arg0, <8 x i32> %arg1, <4 x float> %arg2, i32 %scale0, i32 %scale1) {
140 %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v8i32.v8i32(<8 x i32> %arg0, <8 x i32> %arg1, <4 x float> %arg2,
141 i32 0, ; cbsz
142 i32 5, ; blgp
143 i32 0, i32 %scale0, i32 0, i32 %scale1)
144 ret <4 x float> %result
145 }
147 ; CHECK: invalid value for cbsz format
148 ; CHECK-NEXT: %result = call <16 x float> @llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.v8i32.v8i32(<8 x i32> %arg0, <8 x i32> %arg1, <16 x float> %arg2, i32 5, i32 5, i32 0, i32 %scale0, i32 0, i32 %scale1)
149 ; CHECK-NEXT: i32 5
150 define <16 x float> @test_mfma_scale_f32_32x32x64_f8f6f4___v8i32_invalid__v8i32_invalid(<8 x i32> %arg0, <8 x i32> %arg1, <16 x float> %arg2, i32 %scale0, i32 %scale1) {
151 %result = call <16 x float> @llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.v8i32.v8i32(<8 x i32> %arg0, <8 x i32> %arg1, <16 x float> %arg2,
152 i32 5, ; cbsz
153 i32 5, ; blgp
154 i32 0, i32 %scale0, i32 0, i32 %scale1)
155 ret <16 x float> %result
156 }
158 ; --------------------------------------------------------------------
159 ; Incorrect signature for format cases (IR vector too small)
160 ; --------------------------------------------------------------------
162 ; CHECK: invalid vector type for format
163 ; CHECK-NEXT: %result = call <16 x float> @llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.v4i32.v8i32(<4 x i32> %arg0, <8 x i32> %arg1, <16 x float> %arg2, i32 0, i32 0, i32 0, i32 %scale0, i32 0, i32 %scale1)
164 ; CHECK-NEXT: <4 x i32> %arg0
165 ; CHECK-NEXT: i32 0
166 define <16 x float> @test_mfma_scale_f32_32x32x64_f8f6f4___v4i32_fp8__v8i32_fp8(<4 x i32> %arg0, <8 x i32> %arg1, <16 x float> %arg2, i32 %scale0, i32 %scale1) {
167 %result = call <16 x float> @llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.v4i32.v8i32(<4 x i32> %arg0, <8 x i32> %arg1, <16 x float> %arg2,
168 i32 0, ; cbsz
169 i32 0, ; blgp
170 i32 0, i32 %scale0, i32 0, i32 %scale1)
171 ret <16 x float> %result
172 }
174 ; CHECK: invalid vector type for format
175 ; CHECK-NEXT: %result = call <16 x float> @llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.v8i32.v4i32(<8 x i32> %arg0, <4 x i32> %arg1, <16 x float> %arg2, i32 0, i32 0, i32 0, i32 %scale0, i32 0, i32 %scale1)
176 ; CHECK-NEXT: <4 x i32> %arg1
177 ; CHECK-NEXT: i32 0
178 define <16 x float> @test_mfma_scale_f32_32x32x64_f8f6f4__v8i32_fp8___v4i32_fp8(<8 x i32> %arg0, <4 x i32> %arg1, <16 x float> %arg2, i32 %scale0, i32 %scale1) {
179 %result = call <16 x float> @llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.v8i32.v4i32(<8 x i32> %arg0, <4 x i32> %arg1, <16 x float> %arg2,
180 i32 0, ; cbsz
181 i32 0, ; blgp
182 i32 0, i32 %scale0, i32 0, i32 %scale1)
183 ret <16 x float> %result
184 }
186 ; CHECK: invalid vector type for format
187 ; CHECK-NEXT: %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v4i32.v4i32(<4 x i32> %arg0, <4 x i32> %arg1, <4 x float> %arg2, i32 0, i32 0, i32 0, i32 %scale0, i32 0, i32 %scale1)
188 ; CHECK-NEXT: <4 x i32> %arg0
189 define <4 x float> @test_mfma_scale_f32_16x16x128_f8f6f4___v4i32_fp8__v4i32_fp8(<4 x i32> %arg0, <4 x i32> %arg1, <4 x float> %arg2, i32 %scale0, i32 %scale1) {
190 %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v4i32.v4i32(<4 x i32> %arg0, <4 x i32> %arg1, <4 x float> %arg2,
191 i32 0, ; cbsz
192 i32 0, ; blgp
193 i32 0, i32 %scale0, i32 0, i32 %scale1)
194 ret <4 x float> %result
195 }
197 ; CHECK: invalid vector type for format
198 ; CHECK-NEXT: %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v6i32.v6i32(<6 x i32> %arg0, <6 x i32> %arg1, <4 x float> %arg2, i32 0, i32 0, i32 0, i32 %scale0, i32 0, i32 %scale1)
199 ; CHECK-NEXT: <6 x i32> %arg0
200 define <4 x float> @test_mfma_scale_f32_16x16x128_f8f6f4___v6i32_fp8__v6i32_fp8(<6 x i32> %arg0, <6 x i32> %arg1, <4 x float> %arg2, i32 %scale0, i32 %scale1) {
201 %result = call <4 x float> @llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.v6i32.v6i32(<6 x i32> %arg0, <6 x i32> %arg1, <4 x float> %arg2,
202 i32 0, ; cbsz
203 i32 0, ; blgp
204 i32 0, i32 %scale0, i32 0, i32 %scale1)
205 ret <4 x float> %result
206 }
208 ; CHECK: invalid vector type for format
209 ; CHECK-NEXT: %result = call <16 x float> @llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.v4i32.v4i32(<4 x i32> %arg0, <4 x i32> %arg1, <16 x float> %arg2, i32 0, i32 0, i32 0, i32 %scale0, i32 0, i32 %scale1)
210 ; CHECK-NEXT: <4 x i32> %arg0
211 ; CHECK-NEXT: i32 0
212 define <16 x float> @test_mfma_scale_f32_32x32x64_f8f6f4___v4i32_fp8__v4i32_fp8(<4 x i32> %arg0, <4 x i32> %arg1, <16 x float> %arg2, i32 %scale0, i32 %scale1) {
213 %result = call <16 x float> @llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.v4i32.v4i32(<4 x i32> %arg0, <4 x i32> %arg1, <16 x float> %arg2,
214 i32 0, ; cbsz
215 i32 0, ; blgp
216 i32 0, i32 %scale0, i32 0, i32 %scale1)
217 ret <16 x float> %result
218 }
220 ; CHECK: invalid vector type for format
221 ; CHECK-NEXT: %result = call <16 x float> @llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.v6i32.v6i32(<6 x i32> %arg0, <6 x i32> %arg1, <16 x float> %arg2, i32 0, i32 0, i32 0, i32 %scale0, i32 0, i32 %scale1)
222 ; CHECK-NEXT: <6 x i32> %arg0
223 ; CHECK-NEXT: i32 0
224 define <16 x float> @test_mfma_scale_f32_32x32x64_f8f6f4___v6i32_fp8__v6i32_fp8(<6 x i32> %arg0, <6 x i32> %arg1, <16 x float> %arg2, i32 %scale0, i32 %scale1) {
225 %result = call <16 x float> @llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.v6i32.v6i32(<6 x i32> %arg0, <6 x i32> %arg1, <16 x float> %arg2,
226 i32 0, ; cbsz
227 i32 0, ; blgp
228 i32 0, i32 %scale0, i32 0, i32 %scale1)
229 ret <16 x float> %result
230 }