llvm/test/tools/llvm-mca/AArch64/Cortex/A55-in-order-retire.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-stats --all-views --iterations=2 < %s | FileCheck %s
   3
   4 sdiv    w12, w21, w0
   5 add     w8, w8, #1
   6 add     w1, w2, w0
   7 add     w3, w4, #1
   8 add     w5, w6, w0
   9 add     w7, w9, w0
  10
  11 # CHECK:      Iterations:        2
  12 # CHECK-NEXT: Instructions:      12
  13 # CHECK-NEXT: Total Cycles:      19
  14 # CHECK-NEXT: Total uOps:        12
  15
  16 # CHECK:      Dispatch Width:    2
  17 # CHECK-NEXT: uOps Per Cycle:    0.63
  18 # CHECK-NEXT: IPC:               0.63
  19 # CHECK-NEXT: Block RThroughput: 8.0
  20
  21 # CHECK:      Instruction Info:
  22 # CHECK-NEXT: [1]: #uOps
  23 # CHECK-NEXT: [2]: Latency
  24 # CHECK-NEXT: [3]: RThroughput
  25 # CHECK-NEXT: [4]: MayLoad
  26 # CHECK-NEXT: [5]: MayStore
  27 # CHECK-NEXT: [6]: HasSideEffects (U)
  28
  29 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  30 # CHECK-NEXT:  1      8     8.00                        sdiv    w12, w21, w0
  31 # CHECK-NEXT:  1      3     0.50                        add     w8, w8, #1
  32 # CHECK-NEXT:  1      3     0.50                        add     w1, w2, w0
  33 # CHECK-NEXT:  1      3     0.50                        add     w3, w4, #1
  34 # CHECK-NEXT:  1      3     0.50                        add     w5, w6, w0
  35 # CHECK-NEXT:  1      3     0.50                        add     w7, w9, w0
  36
  37 # CHECK:      Dynamic Dispatch Stall Cycles:
  38 # CHECK-NEXT: RAT     - Register unavailable:                      0
  39 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
  40 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
  41 # CHECK-NEXT: LQ      - Load queue full:                           0
  42 # CHECK-NEXT: SQ      - Store queue full:                          0
  43 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 1  (5.3%)
  44 # CHECK-NEXT: USH     - Uncategorised Structural Hazard:           0
  45
  46 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
  47 # CHECK-NEXT: [# dispatched], [# cycles]
  48 # CHECK-NEXT:  0,              11  (57.9%)
  49 # CHECK-NEXT:  1,              4  (21.1%)
  50 # CHECK-NEXT:  2,              4  (21.1%)
  51
  52 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
  53 # CHECK-NEXT: [# issued], [# cycles]
  54 # CHECK-NEXT:  0,          11  (57.9%)
  55 # CHECK-NEXT:  1,          4  (21.1%)
  56 # CHECK-NEXT:  2,          4  (21.1%)
  57
  58 # CHECK:      Scheduler's queue usage:
  59 # CHECK-NEXT: No scheduler resources used.
  60
  61 # CHECK:      Register File statistics:
  62 # CHECK-NEXT: Total number of mappings created:    12
  63 # CHECK-NEXT: Max number of mappings used:         6
  64
  65 # CHECK:      Resources:
  66 # CHECK-NEXT: [0.0] - CortexA55UnitALU
  67 # CHECK-NEXT: [0.1] - CortexA55UnitALU
  68 # CHECK-NEXT: [1]   - CortexA55UnitB
  69 # CHECK-NEXT: [2]   - CortexA55UnitDiv
  70 # CHECK-NEXT: [3.0] - CortexA55UnitFPALU
  71 # CHECK-NEXT: [3.1] - CortexA55UnitFPALU
  72 # CHECK-NEXT: [4]   - CortexA55UnitFPDIV
  73 # CHECK-NEXT: [5.0] - CortexA55UnitFPMAC
  74 # CHECK-NEXT: [5.1] - CortexA55UnitFPMAC
  75 # CHECK-NEXT: [6]   - CortexA55UnitLd
  76 # CHECK-NEXT: [7]   - CortexA55UnitMAC
  77 # CHECK-NEXT: [8]   - CortexA55UnitSt
  78
  79 # CHECK:      Resource pressure per iteration:
  80 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3.0]  [3.1]  [4]    [5.0]  [5.1]  [6]    [7]    [8]
  81 # CHECK-NEXT: 2.50   2.50    -     8.00    -      -      -      -      -      -      -      -
  82
  83 # CHECK:      Resource pressure by instruction:
  84 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3.0]  [3.1]  [4]    [5.0]  [5.1]  [6]    [7]    [8]    Instructions:
  85 # CHECK-NEXT:  -      -      -     8.00    -      -      -      -      -      -      -      -     sdiv  w12, w21, w0
  86 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -     add   w8, w8, #1
  87 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -     add   w1, w2, w0
  88 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -     add   w3, w4, #1
  89 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -     add   w5, w6, w0
  90 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -     add   w7, w9, w0
  91
  92 # CHECK:      Timeline view:
  93 # CHECK-NEXT:                     012345678
  94 # CHECK-NEXT: Index     0123456789
  95
  96 # CHECK:      [0,0]     DeeeeeeeE .    .  .   sdiv      w12, w21, w0
  97 # CHECK-NEXT: [0,1]     .    DeeE .    .  .   add       w8, w8, #1
  98 # CHECK-NEXT: [0,2]     .    DeeE .    .  .   add       w1, w2, w0
  99 # CHECK-NEXT: [0,3]     .    .DeeE.    .  .   add       w3, w4, #1
 100 # CHECK-NEXT: [0,4]     .    .DeeE.    .  .   add       w5, w6, w0
 101 # CHECK-NEXT: [0,5]     .    . DeeE    .  .   add       w7, w9, w0
 102 # CHECK-NEXT: [1,0]     .    .  DeeeeeeeE .   sdiv      w12, w21, w0
 103 # CHECK-NEXT: [1,1]     .    .    .  DeeE .   add       w8, w8, #1
 104 # CHECK-NEXT: [1,2]     .    .    .  DeeE .   add       w1, w2, w0
 105 # CHECK-NEXT: [1,3]     .    .    .   DeeE.   add       w3, w4, #1
 106 # CHECK-NEXT: [1,4]     .    .    .   DeeE.   add       w5, w6, w0
 107 # CHECK-NEXT: [1,5]     .    .    .    DeeE   add       w7, w9, w0
 108
 109 # CHECK:      Average Wait times (based on the timeline view):
 110 # CHECK-NEXT: [0]: Executions
 111 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 112 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 113 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 114
 115 # CHECK:            [0]    [1]    [2]    [3]
 116 # CHECK-NEXT: 0.     2     0.0    0.0    0.0       sdiv w12, w21, w0
 117 # CHECK-NEXT: 1.     2     0.0    0.0    0.0       add  w8, w8, #1
 118 # CHECK-NEXT: 2.     2     0.0    0.0    0.0       add  w1, w2, w0
 119 # CHECK-NEXT: 3.     2     0.0    0.0    0.0       add  w3, w4, #1
 120 # CHECK-NEXT: 4.     2     0.0    0.0    0.0       add  w5, w6, w0
 121 # CHECK-NEXT: 5.     2     0.0    0.0    0.0       add  w7, w9, w0
 122 # CHECK-NEXT:        2     0.0    0.0    0.0       <total>