llvm/test/tools/llvm-mca/AArch64/Exynos/load.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M3
   3 # RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
   4 # RUN: llvm-mca -march=aarch64 -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M5
   5
   6 ldr     w0, 1f
   7 ldur    x0, [sp, #8]
   8 ldrb    w0, [sp], #1
   9 ldrsh   w0, [sp, #2]!
  10 ldr     x0, [sp, #8]
  11 ldrb    w0, [sp, x31]
  12 ldrsh   w0, [sp, x31, lsl #1]
  13 ldr     w0, [sp, w31, sxtw]
  14 ldr     x0, [sp, w31, uxtw #3]
  15 ldnp    w0, w1, [sp, #8]
  16 ldp     x0, x1, [sp], #16
  17 ldpsw   x0, x1, [sp, #8]!
  18
  19 1:
  20
  21 # ALL:      Iterations:        100
  22 # ALL-NEXT: Instructions:      1200
  23 # ALL-NEXT: Total Cycles:      1304
  24
  25 # M3-NEXT:  Total uOps:        1600
  26 # M4-NEXT:  Total uOps:        1400
  27 # M5-NEXT:  Total uOps:        1400
  28
  29 # ALL:      Dispatch Width:    6
  30
  31 # M3-NEXT:  uOps Per Cycle:    1.23
  32 # M4-NEXT:  uOps Per Cycle:    1.07
  33 # M5-NEXT:  uOps Per Cycle:    1.07
  34
  35 # ALL-NEXT: IPC:               0.92
  36 # ALL-NEXT: Block RThroughput: 6.0
  37
  38 # ALL:      Instruction Info:
  39 # ALL-NEXT: [1]: #uOps
  40 # ALL-NEXT: [2]: Latency
  41 # ALL-NEXT: [3]: RThroughput
  42 # ALL-NEXT: [4]: MayLoad
  43 # ALL-NEXT: [5]: MayStore
  44 # ALL-NEXT: [6]: HasSideEffects (U)
  45
  46 # ALL:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  47 # ALL-NEXT:  1      4     0.50    *                   ldr       w0, {{\.?}}Ltmp0
  48 # ALL-NEXT:  1      4     0.50    *                   ldur      x0, [sp, #8]
  49 # ALL-NEXT:  1      4     0.50    *                   ldrb      w0, [sp], #1
  50 # ALL-NEXT:  1      4     0.50    *                   ldrsh     w0, [sp, #2]!
  51 # ALL-NEXT:  1      4     0.50    *                   ldr       x0, [sp, #8]
  52 # ALL-NEXT:  1      4     0.50    *                   ldrb      w0, [sp, xzr]
  53 # ALL-NEXT:  1      5     0.50    *                   ldrsh     w0, [sp, xzr, lsl #1]
  54
  55 # M3-NEXT:   2      5     0.50    *                   ldr       w0, [sp, wzr, sxtw]
  56 # M3-NEXT:   2      5     0.50    *                   ldr       x0, [sp, wzr, uxtw #3]
  57
  58 # M4-NEXT:   1      5     0.50    *                   ldr       w0, [sp, wzr, sxtw]
  59 # M4-NEXT:   1      5     0.50    *                   ldr       x0, [sp, wzr, uxtw #3]
  60
  61 # M5-NEXT:   1      5     0.50    *                   ldr       w0, [sp, wzr, sxtw]
  62 # M5-NEXT:   1      5     0.50    *                   ldr       x0, [sp, wzr, uxtw #3]
  63
  64 # ALL-NEXT:  1      4     0.50    *                   ldnp      w0, w1, [sp, #8]
  65 # ALL-NEXT:  2      4     0.50    *                   ldp       x0, x1, [sp], #16
  66 # ALL-NEXT:  2      4     0.50    *                   ldpsw     x0, x1, [sp, #8]!