| blob | c4934f4ab02095ae72897af6eb746c215ad1a0a2 |
1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
31 # CHECK: Iterations: 1
32 # CHECK-NEXT: Instructions: 18
33 # CHECK-NEXT: Total Cycles: 125
34 # CHECK-NEXT: Total uOps: 18
36 # CHECK: Dispatch Width: 3
37 # CHECK-NEXT: uOps Per Cycle: 0.14
38 # CHECK-NEXT: IPC: 0.14
39 # CHECK-NEXT: Block RThroughput: 121.0
41 # CHECK: Instruction Info:
42 # CHECK-NEXT: [1]: #uOps
43 # CHECK-NEXT: [2]: Latency
44 # CHECK-NEXT: [3]: RThroughput
45 # CHECK-NEXT: [4]: MayLoad
46 # CHECK-NEXT: [5]: MayStore
47 # CHECK-NEXT: [6]: HasSideEffects (U)
49 # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
50 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
51 # CHECK-NEXT: 1 11 11.00 vslidedown.vx v5, v7, t1
52 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
53 # CHECK-NEXT: 1 14 14.00 vslidedown.vx v5, v7, t1
54 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
55 # CHECK-NEXT: 1 20 20.00 vslidedown.vx v5, v7, t1
56 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
57 # CHECK-NEXT: 1 10 10.00 vslideup.vx v5, v7, t1
58 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
59 # CHECK-NEXT: 1 12 12.00 vslideup.vx v5, v7, t1
60 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
61 # CHECK-NEXT: 1 16 16.00 vslideup.vx v5, v7, t1
62 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
63 # CHECK-NEXT: 1 10 10.00 vslideup.vx v5, v7, t1, v0.t
64 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
65 # CHECK-NEXT: 1 12 12.00 vslideup.vx v5, v7, t1, v0.t
66 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
67 # CHECK-NEXT: 1 16 16.00 vslideup.vx v5, v7, t1, v0.t
69 # CHECK: Resources:
70 # CHECK-NEXT: [0] - SiFiveP400Div
71 # CHECK-NEXT: [1] - SiFiveP400FEXQ0
72 # CHECK-NEXT: [2] - SiFiveP400FloatDiv
73 # CHECK-NEXT: [3] - SiFiveP400IEXQ0
74 # CHECK-NEXT: [4] - SiFiveP400IEXQ1
75 # CHECK-NEXT: [5] - SiFiveP400IEXQ2
76 # CHECK-NEXT: [6] - SiFiveP400Load
77 # CHECK-NEXT: [7] - SiFiveP400Store
78 # CHECK-NEXT: [8] - SiFiveP400VDiv
79 # CHECK-NEXT: [9] - SiFiveP400VEXQ0
80 # CHECK-NEXT: [10] - SiFiveP400VFloatDiv
81 # CHECK-NEXT: [11] - SiFiveP400VLD
82 # CHECK-NEXT: [12] - SiFiveP400VST
84 # CHECK: Resource pressure per iteration:
85 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
86 # CHECK-NEXT: - - - - 9.00 - - - - 121.00 - - -
88 # CHECK: Resource pressure by instruction:
89 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
90 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
91 # CHECK-NEXT: - - - - - - - - - 11.00 - - - vslidedown.vx v5, v7, t1
92 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
93 # CHECK-NEXT: - - - - - - - - - 14.00 - - - vslidedown.vx v5, v7, t1
94 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
95 # CHECK-NEXT: - - - - - - - - - 20.00 - - - vslidedown.vx v5, v7, t1
96 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
97 # CHECK-NEXT: - - - - - - - - - 10.00 - - - vslideup.vx v5, v7, t1
98 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
99 # CHECK-NEXT: - - - - - - - - - 12.00 - - - vslideup.vx v5, v7, t1
100 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
101 # CHECK-NEXT: - - - - - - - - - 16.00 - - - vslideup.vx v5, v7, t1
102 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
103 # CHECK-NEXT: - - - - - - - - - 10.00 - - - vslideup.vx v5, v7, t1, v0.t
104 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
105 # CHECK-NEXT: - - - - - - - - - 12.00 - - - vslideup.vx v5, v7, t1, v0.t
106 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
107 # CHECK-NEXT: - - - - - - - - - 16.00 - - - vslideup.vx v5, v7, t1, v0.t