| blob | 285d21cbd33d53f72963a05a91b6a1f5dbb92a48 |
2 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
3 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
5 # SEW is only e32 or e64
47 # CHECK: Iterations: 1
48 # CHECK-NEXT: Instructions: 32
49 # CHECK-NEXT: Total Cycles: 102
50 # CHECK-NEXT: Total uOps: 32
52 # CHECK: Dispatch Width: 3
53 # CHECK-NEXT: uOps Per Cycle: 0.31
54 # CHECK-NEXT: IPC: 0.31
55 # CHECK-NEXT: Block RThroughput: 90.0
57 # CHECK: Instruction Info:
58 # CHECK-NEXT: [1]: #uOps
59 # CHECK-NEXT: [2]: Latency
60 # CHECK-NEXT: [3]: RThroughput
61 # CHECK-NEXT: [4]: MayLoad
62 # CHECK-NEXT: [5]: MayStore
63 # CHECK-NEXT: [6]: HasSideEffects (U)
65 # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
66 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
67 # CHECK-NEXT: 1 3 1.00 vsha2ms.vv v4, v8, v12
68 # CHECK-NEXT: 1 3 1.00 vsha2ch.vv v4, v8, v12
69 # CHECK-NEXT: 1 3 1.00 vsha2cl.vv v4, v8, v12
70 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
71 # CHECK-NEXT: 1 3 2.00 vsha2ms.vv v4, v8, v12
72 # CHECK-NEXT: 1 3 2.00 vsha2ch.vv v4, v8, v12
73 # CHECK-NEXT: 1 3 2.00 vsha2cl.vv v4, v8, v12
74 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
75 # CHECK-NEXT: 1 3 4.00 vsha2ms.vv v4, v8, v12
76 # CHECK-NEXT: 1 3 4.00 vsha2ch.vv v4, v8, v12
77 # CHECK-NEXT: 1 3 4.00 vsha2cl.vv v4, v8, v12
78 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
79 # CHECK-NEXT: 1 3 8.00 vsha2ms.vv v8, v16, v24
80 # CHECK-NEXT: 1 3 8.00 vsha2ch.vv v8, v16, v24
81 # CHECK-NEXT: 1 3 8.00 vsha2cl.vv v8, v16, v24
82 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
83 # CHECK-NEXT: 1 3 1.00 vsha2ms.vv v4, v8, v12
84 # CHECK-NEXT: 1 3 1.00 vsha2ch.vv v4, v8, v12
85 # CHECK-NEXT: 1 3 1.00 vsha2cl.vv v4, v8, v12
86 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
87 # CHECK-NEXT: 1 3 2.00 vsha2ms.vv v4, v8, v12
88 # CHECK-NEXT: 1 3 2.00 vsha2ch.vv v4, v8, v12
89 # CHECK-NEXT: 1 3 2.00 vsha2cl.vv v4, v8, v12
90 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
91 # CHECK-NEXT: 1 3 4.00 vsha2ms.vv v4, v8, v12
92 # CHECK-NEXT: 1 3 4.00 vsha2ch.vv v4, v8, v12
93 # CHECK-NEXT: 1 3 4.00 vsha2cl.vv v4, v8, v12
94 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
95 # CHECK-NEXT: 1 3 8.00 vsha2ms.vv v8, v16, v24
96 # CHECK-NEXT: 1 3 8.00 vsha2ch.vv v8, v16, v24
97 # CHECK-NEXT: 1 3 8.00 vsha2cl.vv v8, v16, v24
99 # CHECK: Resources:
100 # CHECK-NEXT: [0] - SiFiveP400Div
101 # CHECK-NEXT: [1] - SiFiveP400FEXQ0
102 # CHECK-NEXT: [2] - SiFiveP400FloatDiv
103 # CHECK-NEXT: [3] - SiFiveP400IEXQ0
104 # CHECK-NEXT: [4] - SiFiveP400IEXQ1
105 # CHECK-NEXT: [5] - SiFiveP400IEXQ2
106 # CHECK-NEXT: [6] - SiFiveP400Load
107 # CHECK-NEXT: [7] - SiFiveP400Store
108 # CHECK-NEXT: [8] - SiFiveP400VDiv
109 # CHECK-NEXT: [9] - SiFiveP400VEXQ0
110 # CHECK-NEXT: [10] - SiFiveP400VFloatDiv
111 # CHECK-NEXT: [11] - SiFiveP400VLD
112 # CHECK-NEXT: [12] - SiFiveP400VST
114 # CHECK: Resource pressure per iteration:
115 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
116 # CHECK-NEXT: - - - - 8.00 - - - - 90.00 - - -
118 # CHECK: Resource pressure by instruction:
119 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
120 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
121 # CHECK-NEXT: - - - - - - - - - 1.00 - - - vsha2ms.vv v4, v8, v12
122 # CHECK-NEXT: - - - - - - - - - 1.00 - - - vsha2ch.vv v4, v8, v12
123 # CHECK-NEXT: - - - - - - - - - 1.00 - - - vsha2cl.vv v4, v8, v12
124 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
125 # CHECK-NEXT: - - - - - - - - - 2.00 - - - vsha2ms.vv v4, v8, v12
126 # CHECK-NEXT: - - - - - - - - - 2.00 - - - vsha2ch.vv v4, v8, v12
127 # CHECK-NEXT: - - - - - - - - - 2.00 - - - vsha2cl.vv v4, v8, v12
128 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
129 # CHECK-NEXT: - - - - - - - - - 4.00 - - - vsha2ms.vv v4, v8, v12
130 # CHECK-NEXT: - - - - - - - - - 4.00 - - - vsha2ch.vv v4, v8, v12
131 # CHECK-NEXT: - - - - - - - - - 4.00 - - - vsha2cl.vv v4, v8, v12
132 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
133 # CHECK-NEXT: - - - - - - - - - 8.00 - - - vsha2ms.vv v8, v16, v24
134 # CHECK-NEXT: - - - - - - - - - 8.00 - - - vsha2ch.vv v8, v16, v24
135 # CHECK-NEXT: - - - - - - - - - 8.00 - - - vsha2cl.vv v8, v16, v24
136 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
137 # CHECK-NEXT: - - - - - - - - - 1.00 - - - vsha2ms.vv v4, v8, v12
138 # CHECK-NEXT: - - - - - - - - - 1.00 - - - vsha2ch.vv v4, v8, v12
139 # CHECK-NEXT: - - - - - - - - - 1.00 - - - vsha2cl.vv v4, v8, v12
140 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
141 # CHECK-NEXT: - - - - - - - - - 2.00 - - - vsha2ms.vv v4, v8, v12
142 # CHECK-NEXT: - - - - - - - - - 2.00 - - - vsha2ch.vv v4, v8, v12
143 # CHECK-NEXT: - - - - - - - - - 2.00 - - - vsha2cl.vv v4, v8, v12
144 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
145 # CHECK-NEXT: - - - - - - - - - 4.00 - - - vsha2ms.vv v4, v8, v12
146 # CHECK-NEXT: - - - - - - - - - 4.00 - - - vsha2ch.vv v4, v8, v12
147 # CHECK-NEXT: - - - - - - - - - 4.00 - - - vsha2cl.vv v4, v8, v12
148 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
149 # CHECK-NEXT: - - - - - - - - - 8.00 - - - vsha2ms.vv v8, v16, v24
150 # CHECK-NEXT: - - - - - - - - - 8.00 - - - vsha2ch.vv v8, v16, v24
151 # CHECK-NEXT: - - - - - - - - - 8.00 - - - vsha2cl.vv v8, v16, v24