ELF: Have __rela_iplt_{start,end} surround .rela.iplt with --pack-dyn-relocs=android.
[llvm-project.git] / llvm / test / tools / llvm-mca / RISCV / SiFiveP400 / zvksed.s
blob127998f34aa38a7bbf9d262e14abf37e7f2b3ebd
2 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
3 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
5 # These instructions only support e32
7 vsetvli zero, zero, e32, mf2, tu, mu
8 vsm4k.vi v4, v8, 8
9 vsm4r.vv v4, v8
10 vsm4r.vs v4, v8
12 vsetvli zero, zero, e32, m1, tu, mu
13 vsm4k.vi v4, v8, 8
14 vsm4r.vv v4, v8
15 vsm4r.vs v4, v8
17 vsetvli zero, zero, e32, m2, tu, mu
18 vsm4k.vi v4, v8, 8
19 vsm4r.vv v4, v8
20 vsm4r.vs v4, v8
22 vsetvli zero, zero, e32, m4, tu, mu
23 vsm4k.vi v4, v8, 8
24 vsm4r.vv v4, v8
25 vsm4r.vs v4, v8
27 vsetvli zero, zero, e32, m8, tu, mu
28 vsm4k.vi v8, v16, 8
29 vsm4r.vv v8, v16
30 vsm4r.vs v8, v16
32 # CHECK: Iterations: 1
33 # CHECK-NEXT: Instructions: 20
34 # CHECK-NEXT: Total Cycles: 47
35 # CHECK-NEXT: Total uOps: 20
37 # CHECK: Dispatch Width: 3
38 # CHECK-NEXT: uOps Per Cycle: 0.43
39 # CHECK-NEXT: IPC: 0.43
40 # CHECK-NEXT: Block RThroughput: 48.0
42 # CHECK: Instruction Info:
43 # CHECK-NEXT: [1]: #uOps
44 # CHECK-NEXT: [2]: Latency
45 # CHECK-NEXT: [3]: RThroughput
46 # CHECK-NEXT: [4]: MayLoad
47 # CHECK-NEXT: [5]: MayStore
48 # CHECK-NEXT: [6]: HasSideEffects (U)
50 # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
51 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
52 # CHECK-NEXT: 1 3 1.00 vsm4k.vi v4, v8, 8
53 # CHECK-NEXT: 1 3 1.00 vsm4r.vv v4, v8
54 # CHECK-NEXT: 1 3 1.00 vsm4r.vs v4, v8
55 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
56 # CHECK-NEXT: 1 3 1.00 vsm4k.vi v4, v8, 8
57 # CHECK-NEXT: 1 3 1.00 vsm4r.vv v4, v8
58 # CHECK-NEXT: 1 3 1.00 vsm4r.vs v4, v8
59 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
60 # CHECK-NEXT: 1 3 2.00 vsm4k.vi v4, v8, 8
61 # CHECK-NEXT: 1 3 2.00 vsm4r.vv v4, v8
62 # CHECK-NEXT: 1 3 2.00 vsm4r.vs v4, v8
63 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
64 # CHECK-NEXT: 1 3 4.00 vsm4k.vi v4, v8, 8
65 # CHECK-NEXT: 1 3 4.00 vsm4r.vv v4, v8
66 # CHECK-NEXT: 1 3 4.00 vsm4r.vs v4, v8
67 # CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
68 # CHECK-NEXT: 1 3 8.00 vsm4k.vi v8, v16, 8
69 # CHECK-NEXT: 1 3 8.00 vsm4r.vv v8, v16
70 # CHECK-NEXT: 1 3 8.00 vsm4r.vs v8, v16
72 # CHECK: Resources:
73 # CHECK-NEXT: [0] - SiFiveP400Div
74 # CHECK-NEXT: [1] - SiFiveP400FEXQ0
75 # CHECK-NEXT: [2] - SiFiveP400FloatDiv
76 # CHECK-NEXT: [3] - SiFiveP400IEXQ0
77 # CHECK-NEXT: [4] - SiFiveP400IEXQ1
78 # CHECK-NEXT: [5] - SiFiveP400IEXQ2
79 # CHECK-NEXT: [6] - SiFiveP400Load
80 # CHECK-NEXT: [7] - SiFiveP400Store
81 # CHECK-NEXT: [8] - SiFiveP400VDiv
82 # CHECK-NEXT: [9] - SiFiveP400VEXQ0
83 # CHECK-NEXT: [10] - SiFiveP400VFloatDiv
84 # CHECK-NEXT: [11] - SiFiveP400VLD
85 # CHECK-NEXT: [12] - SiFiveP400VST
87 # CHECK: Resource pressure per iteration:
88 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
89 # CHECK-NEXT: - - - - 5.00 - - - - 48.00 - - -
91 # CHECK: Resource pressure by instruction:
92 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
93 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
94 # CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm4k.vi v4, v8, 8
95 # CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm4r.vv v4, v8
96 # CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm4r.vs v4, v8
97 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
98 # CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm4k.vi v4, v8, 8
99 # CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm4r.vv v4, v8
100 # CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm4r.vs v4, v8
101 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
102 # CHECK-NEXT: - - - - - - - - - 2.00 - - - vsm4k.vi v4, v8, 8
103 # CHECK-NEXT: - - - - - - - - - 2.00 - - - vsm4r.vv v4, v8
104 # CHECK-NEXT: - - - - - - - - - 2.00 - - - vsm4r.vs v4, v8
105 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
106 # CHECK-NEXT: - - - - - - - - - 4.00 - - - vsm4k.vi v4, v8, 8
107 # CHECK-NEXT: - - - - - - - - - 4.00 - - - vsm4r.vv v4, v8
108 # CHECK-NEXT: - - - - - - - - - 4.00 - - - vsm4r.vs v4, v8
109 # CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
110 # CHECK-NEXT: - - - - - - - - - 8.00 - - - vsm4k.vi v8, v16, 8
111 # CHECK-NEXT: - - - - - - - - - 8.00 - - - vsm4r.vv v8, v16
112 # CHECK-NEXT: - - - - - - - - - 8.00 - - - vsm4r.vs v8, v16