llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvksh.s

   1
   2 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   3 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
   4
   5 # These instructions only support e32
   6
   7 vsetvli zero, zero, e32, mf2, tu, mu
   8 vsm3me.vv v4, v8, v12
   9 vsm3c.vi v4, v8, 8
  10
  11 vsetvli zero, zero, e32, m1, tu, mu
  12 vsm3me.vv v4, v8, v12
  13 vsm3c.vi v4, v8, 8
  14
  15 vsetvli zero, zero, e32, m2, tu, mu
  16 vsm3me.vv v4, v8, v12
  17 vsm3c.vi v4, v8, 8
  18
  19 vsetvli zero, zero, e32, m4, tu, mu
  20 vsm3me.vv v4, v8, v12
  21 vsm3c.vi v4, v8, 8
  22
  23 vsetvli zero, zero, e32, m8, tu, mu
  24 vsm3me.vv v8, v16, v24
  25 vsm3c.vi  v8, v16, 8
  26
  27 # CHECK:      Iterations:        1
  28 # CHECK-NEXT: Instructions:      15
  29 # CHECK-NEXT: Total Cycles:      28
  30 # CHECK-NEXT: Total uOps:        15
  31
  32 # CHECK:      Dispatch Width:    3
  33 # CHECK-NEXT: uOps Per Cycle:    0.54
  34 # CHECK-NEXT: IPC:               0.54
  35 # CHECK-NEXT: Block RThroughput: 25.0
  36
  37 # CHECK:      Instruction Info:
  38 # CHECK-NEXT: [1]: #uOps
  39 # CHECK-NEXT: [2]: Latency
  40 # CHECK-NEXT: [3]: RThroughput
  41 # CHECK-NEXT: [4]: MayLoad
  42 # CHECK-NEXT: [5]: MayStore
  43 # CHECK-NEXT: [6]: HasSideEffects (U)
  44
  45 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  46 # CHECK-NEXT:  1      1     1.00                  U     vsetvli zero, zero, e32, mf2, tu, mu
  47 # CHECK-NEXT:  1      6     1.00                        vsm3me.vv v4, v8, v12
  48 # CHECK-NEXT:  1      3     1.00                        vsm3c.vi  v4, v8, 8
  49 # CHECK-NEXT:  1      1     1.00                  U     vsetvli zero, zero, e32, m1, tu, mu
  50 # CHECK-NEXT:  1      6     1.00                        vsm3me.vv v4, v8, v12
  51 # CHECK-NEXT:  1      3     1.00                        vsm3c.vi  v4, v8, 8
  52 # CHECK-NEXT:  1      1     1.00                  U     vsetvli zero, zero, e32, m2, tu, mu
  53 # CHECK-NEXT:  1      6     2.00                        vsm3me.vv v4, v8, v12
  54 # CHECK-NEXT:  1      3     1.00                        vsm3c.vi  v4, v8, 8
  55 # CHECK-NEXT:  1      1     1.00                  U     vsetvli zero, zero, e32, m4, tu, mu
  56 # CHECK-NEXT:  1      6     4.00                        vsm3me.vv v4, v8, v12
  57 # CHECK-NEXT:  1      3     2.00                        vsm3c.vi  v4, v8, 8
  58 # CHECK-NEXT:  1      1     1.00                  U     vsetvli zero, zero, e32, m8, tu, mu
  59 # CHECK-NEXT:  1      6     8.00                        vsm3me.vv v8, v16, v24
  60 # CHECK-NEXT:  1      3     4.00                        vsm3c.vi  v8, v16, 8
  61
  62 # CHECK:      Resources:
  63 # CHECK-NEXT: [0]   - SiFiveP400Div
  64 # CHECK-NEXT: [1]   - SiFiveP400FEXQ0
  65 # CHECK-NEXT: [2]   - SiFiveP400FloatDiv
  66 # CHECK-NEXT: [3]   - SiFiveP400IEXQ0
  67 # CHECK-NEXT: [4]   - SiFiveP400IEXQ1
  68 # CHECK-NEXT: [5]   - SiFiveP400IEXQ2
  69 # CHECK-NEXT: [6]   - SiFiveP400Load
  70 # CHECK-NEXT: [7]   - SiFiveP400Store
  71 # CHECK-NEXT: [8]   - SiFiveP400VDiv
  72 # CHECK-NEXT: [9]   - SiFiveP400VEXQ0
  73 # CHECK-NEXT: [10]  - SiFiveP400VFloatDiv
  74 # CHECK-NEXT: [11]  - SiFiveP400VLD
  75 # CHECK-NEXT: [12]  - SiFiveP400VST
  76
  77 # CHECK:      Resource pressure per iteration:
  78 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]
  79 # CHECK-NEXT:  -      -      -      -     5.00    -      -      -      -     25.00   -      -      -
  80
  81 # CHECK:      Resource pressure by instruction:
  82 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   Instructions:
  83 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -      -      -      -      -      -     vsetvli  zero, zero, e32, mf2, tu, mu
  84 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     1.00    -      -      -     vsm3me.vv  v4, v8, v12
  85 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     1.00    -      -      -     vsm3c.vi v4, v8, 8
  86 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -      -      -      -      -      -     vsetvli  zero, zero, e32, m1, tu, mu
  87 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     1.00    -      -      -     vsm3me.vv  v4, v8, v12
  88 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     1.00    -      -      -     vsm3c.vi v4, v8, 8
  89 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -      -      -      -      -      -     vsetvli  zero, zero, e32, m2, tu, mu
  90 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     2.00    -      -      -     vsm3me.vv  v4, v8, v12
  91 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     1.00    -      -      -     vsm3c.vi v4, v8, 8
  92 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -      -      -      -      -      -     vsetvli  zero, zero, e32, m4, tu, mu
  93 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     4.00    -      -      -     vsm3me.vv  v4, v8, v12
  94 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     2.00    -      -      -     vsm3c.vi v4, v8, 8
  95 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -      -      -      -      -      -     vsetvli  zero, zero, e32, m8, tu, mu
  96 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     8.00    -      -      -     vsm3me.vv  v8, v16, v24
  97 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     4.00    -      -      -     vsm3c.vi v8, v16, 8
  98