llvm/test/tools/llvm-mca/RISCV/different-lmul-instruments.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
   3
   4 vsetvli zero, a0, e8, m1, tu, mu
   5 # LLVM-MCA-RISCV-LMUL M1
   6 vadd.vv v12, v12, v12
   7 vsetvli zero, a0, e8, m8, tu, mu
   8 # LLVM-MCA-RISCV-LMUL M8
   9 vadd.vv v12, v12, v12
  10
  11 # CHECK:      Iterations:        1
  12 # CHECK-NEXT: Instructions:      4
  13 # CHECK-NEXT: Total Cycles:      12
  14 # CHECK-NEXT: Total uOps:        4
  15
  16 # CHECK:      Dispatch Width:    2
  17 # CHECK-NEXT: uOps Per Cycle:    0.33
  18 # CHECK-NEXT: IPC:               0.33
  19 # CHECK-NEXT: Block RThroughput: 20.0
  20
  21 # CHECK:      Instruction Info:
  22 # CHECK-NEXT: [1]: #uOps
  23 # CHECK-NEXT: [2]: Latency
  24 # CHECK-NEXT: [3]: RThroughput
  25 # CHECK-NEXT: [4]: MayLoad
  26 # CHECK-NEXT: [5]: MayStore
  27 # CHECK-NEXT: [6]: HasSideEffects (U)
  28
  29 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  30 # CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e8, m1, tu, mu
  31 # CHECK-NEXT:  1      4     3.00                        vadd.vv v12, v12, v12
  32 # CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e8, m8, tu, mu
  33 # CHECK-NEXT:  1      4     17.00                       vadd.vv v12, v12, v12
  34
  35 # CHECK:      Resources:
  36 # CHECK-NEXT: [0]   - SiFive7FDiv
  37 # CHECK-NEXT: [1]   - SiFive7IDiv
  38 # CHECK-NEXT: [2]   - SiFive7PipeA
  39 # CHECK-NEXT: [3]   - SiFive7PipeB
  40 # CHECK-NEXT: [4]   - SiFive7VA
  41 # CHECK-NEXT: [5]   - SiFive7VCQ
  42 # CHECK-NEXT: [6]   - SiFive7VL
  43 # CHECK-NEXT: [7]   - SiFive7VS
  44
  45 # CHECK:      Resource pressure per iteration:
  46 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
  47 # CHECK-NEXT:  -      -     2.00    -     20.00  2.00    -      -
  48
  49 # CHECK:      Resource pressure by instruction:
  50 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
  51 # CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli   zero, a0, e8, m1, tu, mu
  52 # CHECK-NEXT:  -      -      -      -     3.00   1.00    -      -     vadd.vv   v12, v12, v12
  53 # CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli   zero, a0, e8, m8, tu, mu
  54 # CHECK-NEXT:  -      -      -      -     17.00  1.00    -      -     vadd.vv   v12, v12, v12
  55
  56 # CHECK:      Timeline view:
  57 # CHECK-NEXT:                     01
  58 # CHECK-NEXT: Index     0123456789
  59
  60 # CHECK:      [0,0]     DeeE .    ..   vsetvli  zero, a0, e8, m1, tu, mu
  61 # CHECK-NEXT: [0,1]     .  DeeeE  ..   vadd.vv  v12, v12, v12
  62 # CHECK-NEXT: [0,2]     .   DeeE  ..   vsetvli  zero, a0, e8, m8, tu, mu
  63 # CHECK-NEXT: [0,3]     .    . DeeeE   vadd.vv  v12, v12, v12
  64
  65 # CHECK:      Average Wait times (based on the timeline view):
  66 # CHECK-NEXT: [0]: Executions
  67 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
  68 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
  69 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
  70
  71 # CHECK:            [0]    [1]    [2]    [3]
  72 # CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli      zero, a0, e8, m1, tu, mu
  73 # CHECK-NEXT: 1.     1     0.0    0.0    0.0       vadd.vv      v12, v12, v12
  74 # CHECK-NEXT: 2.     1     0.0    0.0    0.0       vsetvli      zero, a0, e8, m8, tu, mu
  75 # CHECK-NEXT: 3.     1     0.0    0.0    0.0       vadd.vv      v12, v12, v12
  76 # CHECK-NEXT:        1     0.0    0.0    0.0       <total>