1 # REQUIRES: riscv-registered-target
2 # RUN: llvm-reduce -abort-on-invalid-reduction --delta-passes=instructions -mtriple=riscv32 --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t
3 # RUN: FileCheck --match-full-lines %s < %t
5 # CHECK-INTERESTINGNESS: %{{[0-9]+}}:gpr = ADDI %{{[0-9]+}}, 5
7 # Verify that after reduction the following instruction sequence remains. The
8 # interestingness-test 'instr-reduce.py' matches a '%[0-9]+:gpr = ADDI %[0-9]+, 5'
9 # pattern in the output and that combined with that the MIR has to be valid
10 # (pass verify) results in the given sequence.
12 # CHECK: [[IMPDEF:%[0-9]+]]:gpr = IMPLICIT_DEF
13 # CHECK-NEXT: %{{[0-9]+}}:gpr = ADDI [[IMPDEF]], 5
14 # CHECK-NEXT: PseudoRET implicit $x10
19 tracksRegLiveness: true
29 PseudoRET implicit $x10