llvm/unittests/Target/AMDGPU/CSETest.cpp

   1 //===- llvm/unittests/Target/AMDGPU/CSETest.cpp ---------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #include "AMDGPUTargetMachine.h"
  10 #include "AMDGPUUnitTests.h"
  11 #include "llvm/CodeGen/GlobalISel/CSEInfo.h"
  12 #include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h"
  13 #include "gtest/gtest.h"
  14
  15 using namespace llvm;
  16
  17 TEST(AMDGPU, TestCSEForRegisterClassOrBankAndLLT) {
  18   auto TM = createAMDGPUTargetMachine("amdgcn-amd-", "gfx1100", "");
  19   if (!TM)
  20     GTEST_SKIP();
  21
  22   GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
  23                   std::string(TM->getTargetFeatureString()), *TM);
  24
  25   LLVMContext Ctx;
  26   Module Mod("Module", Ctx);
  27   Mod.setDataLayout(TM->createDataLayout());
  28
  29   auto *Type = FunctionType::get(Type::getVoidTy(Ctx), false);
  30   auto *F = Function::Create(Type, GlobalValue::ExternalLinkage, "Test", &Mod);
  31
  32   MachineModuleInfo MMI(TM.get());
  33   auto MF =
  34       std::make_unique<MachineFunction>(*F, *TM, ST, MMI.getContext(), 42);
  35   auto *BB = MF->CreateMachineBasicBlock();
  36   MF->push_back(BB);
  37
  38   MachineIRBuilder B(*MF);
  39   B.setMBB(*BB);
  40
  41   LLT S32{LLT::scalar(32)};
  42   Register R0 = B.buildCopy(S32, Register(AMDGPU::SGPR0)).getReg(0);
  43   Register R1 = B.buildCopy(S32, Register(AMDGPU::SGPR1)).getReg(0);
  44
  45   GISelCSEInfo CSEInfo;
  46   CSEInfo.setCSEConfig(std::make_unique<CSEConfigFull>());
  47   CSEInfo.analyze(*MF);
  48   B.setCSEInfo(&CSEInfo);
  49   CSEMIRBuilder CSEB(B.getState());
  50   CSEB.setInsertPt(B.getMBB(), B.getInsertPt());
  51
  52   const RegisterBankInfo &RBI = *MF->getSubtarget().getRegBankInfo();
  53
  54   const TargetRegisterClass *SgprRC = &AMDGPU::SReg_32RegClass;
  55   const RegisterBank *SgprRB = &RBI.getRegBank(AMDGPU::SGPRRegBankID);
  56   MachineRegisterInfo::VRegAttrs SgprRCS32 = {SgprRC, S32};
  57   MachineRegisterInfo::VRegAttrs SgprRBS32 = {SgprRB, S32};
  58
  59   auto Add = CSEB.buildAdd(S32, R0, R1);
  60   auto AddRC = CSEB.buildInstr(AMDGPU::G_ADD, {SgprRCS32}, {R0, R1});
  61   auto AddRB = CSEB.buildInstr(AMDGPU::G_ADD, {{SgprRB, S32}}, {R0, R1});
  62
  63   EXPECT_NE(Add, AddRC);
  64   EXPECT_NE(Add, AddRB);
  65   EXPECT_NE(AddRC, AddRB);
  66
  67   auto Add_CSE = CSEB.buildAdd(S32, R0, R1);
  68   auto AddRC_CSE = CSEB.buildInstr(AMDGPU::G_ADD, {{SgprRC, S32}}, {R0, R1});
  69   auto AddRB_CSE = CSEB.buildInstr(AMDGPU::G_ADD, {SgprRBS32}, {R0, R1});
  70
  71   EXPECT_EQ(Add, Add_CSE);
  72   EXPECT_EQ(AddRC, AddRC_CSE);
  73   EXPECT_EQ(AddRB, AddRB_CSE);
  74 }