[gcov] Bump default version to 11.1
[llvm-project.git] / llvm / unittests / TargetParser / Host.cpp
bloba478c2e6d92d3ed0470b98ba8925fb458cc1cbaf
1 //========- unittests/Support/Host.cpp - Host.cpp tests --------------========//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
9 #include "llvm/TargetParser/Host.h"
10 #include "llvm/ADT/SmallVector.h"
11 #include "llvm/Config/config.h"
12 #include "llvm/Support/FileSystem.h"
13 #include "llvm/Support/Path.h"
14 #include "llvm/Support/Program.h"
15 #include "llvm/Support/Threading.h"
16 #include "llvm/TargetParser/Triple.h"
18 #include "gtest/gtest.h"
20 #define ASSERT_NO_ERROR(x) \
21 if (std::error_code ASSERT_NO_ERROR_ec = x) { \
22 SmallString<128> MessageStorage; \
23 raw_svector_ostream Message(MessageStorage); \
24 Message << #x ": did not return errc::success.\n" \
25 << "error number: " << ASSERT_NO_ERROR_ec.value() << "\n" \
26 << "error message: " << ASSERT_NO_ERROR_ec.message() << "\n"; \
27 GTEST_FATAL_FAILURE_(MessageStorage.c_str()); \
28 } else { \
31 using namespace llvm;
33 TEST(getLinuxHostCPUName, ARM) {
34 StringRef CortexA9ProcCpuinfo = R"(
35 processor : 0
36 model name : ARMv7 Processor rev 10 (v7l)
37 BogoMIPS : 1393.66
38 Features : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpd32
39 CPU implementer : 0x41
40 CPU architecture: 7
41 CPU variant : 0x2
42 CPU part : 0xc09
43 CPU revision : 10
45 processor : 1
46 model name : ARMv7 Processor rev 10 (v7l)
47 BogoMIPS : 1393.66
48 Features : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpd32
49 CPU implementer : 0x41
50 CPU architecture: 7
51 CPU variant : 0x2
52 CPU part : 0xc09
53 CPU revision : 10
55 Hardware : Generic OMAP4 (Flattened Device Tree)
56 Revision : 0000
57 Serial : 0000000000000000
58 )";
60 EXPECT_EQ(sys::detail::getHostCPUNameForARM(CortexA9ProcCpuinfo),
61 "cortex-a9");
62 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
63 "CPU part : 0xc0f"),
64 "cortex-a15");
65 // Verify that both CPU implementer and CPU part are checked:
66 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x40\n"
67 "CPU part : 0xc0f"),
68 "generic");
69 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
70 "CPU part : 0x06f"),
71 "krait");
74 TEST(getLinuxHostCPUName, AArch64) {
75 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
76 "CPU part : 0xd03"),
77 "cortex-a53");
78 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
79 "CPU part : 0xd05"),
80 "cortex-a55");
82 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
83 "CPU part : 0xd40"),
84 "neoverse-v1");
85 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
86 "CPU part : 0xd4f"),
87 "neoverse-v2");
88 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
89 "CPU part : 0xd84"),
90 "neoverse-v3");
91 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
92 "CPU part : 0xd0c"),
93 "neoverse-n1");
94 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
95 "CPU part : 0xd49"),
96 "neoverse-n2");
97 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
98 "CPU part : 0xd8e"),
99 "neoverse-n3");
100 // Verify that both CPU implementer and CPU part are checked:
101 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x40\n"
102 "CPU part : 0xd03"),
103 "generic");
104 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
105 "CPU part : 0x201"),
106 "kryo");
107 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
108 "CPU part : 0x800"),
109 "cortex-a73");
110 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
111 "CPU part : 0x801"),
112 "cortex-a73");
113 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
114 "CPU part : 0xd46"),
115 "cortex-a510");
116 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
117 "CPU part : 0xd47"),
118 "cortex-a710");
119 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
120 "CPU part : 0xd48"),
121 "cortex-x2");
122 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
123 "CPU part : 0xc00"),
124 "falkor");
125 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
126 "CPU part : 0xc01"),
127 "saphira");
128 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x6d\n"
129 "CPU part : 0xd49"),
130 "neoverse-n2");
131 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
132 "CPU part : 0xac3"),
133 "ampere1");
134 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
135 "CPU part : 0xac4"),
136 "ampere1a");
137 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
138 "CPU part : 0xac5"),
139 "ampere1b");
140 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
141 "CPU part : 0x001"),
142 "oryon-1");
143 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x46\n"
144 "CPU part : 0x003"),
145 "fujitsu-monaka");
146 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x61\n"
147 "CPU part : 0x039"),
148 "apple-m2");
150 // MSM8992/4 weirdness
151 StringRef MSM8992ProcCpuInfo = R"(
152 Processor : AArch64 Processor rev 3 (aarch64)
153 processor : 0
154 processor : 1
155 processor : 2
156 processor : 3
157 processor : 4
158 processor : 5
159 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
160 CPU implementer : 0x41
161 CPU architecture: 8
162 CPU variant : 0x0
163 CPU part : 0xd03
164 CPU revision : 3
166 Hardware : Qualcomm Technologies, Inc MSM8992
169 EXPECT_EQ(sys::detail::getHostCPUNameForARM(MSM8992ProcCpuInfo),
170 "cortex-a53");
172 // Exynos big.LITTLE weirdness
173 const std::string ExynosProcCpuInfo = R"(
174 processor : 0
175 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
176 CPU implementer : 0x41
177 CPU architecture: 8
178 CPU variant : 0x0
179 CPU part : 0xd05
181 processor : 1
182 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
183 CPU implementer : 0x53
184 CPU architecture: 8
187 // Verify default for Exynos.
188 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ExynosProcCpuInfo +
189 "CPU variant : 0xc\n"
190 "CPU part : 0xafe"),
191 "exynos-m3");
192 // Verify Exynos M3.
193 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ExynosProcCpuInfo +
194 "CPU variant : 0x1\n"
195 "CPU part : 0x002"),
196 "exynos-m3");
197 // Verify Exynos M4.
198 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ExynosProcCpuInfo +
199 "CPU variant : 0x1\n"
200 "CPU part : 0x003"),
201 "exynos-m4");
203 const std::string ThunderX2T99ProcCpuInfo = R"(
204 processor : 0
205 BogoMIPS : 400.00
206 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
207 CPU implementer : 0x43
208 CPU architecture: 8
209 CPU variant : 0x1
210 CPU part : 0x0af
213 // Verify different versions of ThunderX2T99.
214 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderX2T99ProcCpuInfo +
215 "CPU implementer : 0x42\n"
216 "CPU part : 0x516"),
217 "thunderx2t99");
219 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderX2T99ProcCpuInfo +
220 "CPU implementer : 0x42\n"
221 "CPU part : 0x0516"),
222 "thunderx2t99");
224 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderX2T99ProcCpuInfo +
225 "CPU implementer : 0x43\n"
226 "CPU part : 0x516"),
227 "thunderx2t99");
229 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderX2T99ProcCpuInfo +
230 "CPU implementer : 0x43\n"
231 "CPU part : 0x0516"),
232 "thunderx2t99");
234 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderX2T99ProcCpuInfo +
235 "CPU implementer : 0x42\n"
236 "CPU part : 0xaf"),
237 "thunderx2t99");
239 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderX2T99ProcCpuInfo +
240 "CPU implementer : 0x42\n"
241 "CPU part : 0x0af"),
242 "thunderx2t99");
244 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderX2T99ProcCpuInfo +
245 "CPU implementer : 0x43\n"
246 "CPU part : 0xaf"),
247 "thunderx2t99");
249 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderX2T99ProcCpuInfo +
250 "CPU implementer : 0x43\n"
251 "CPU part : 0x0af"),
252 "thunderx2t99");
254 // Verify ThunderXT88.
255 const std::string ThunderXT88ProcCpuInfo = R"(
256 processor : 0
257 BogoMIPS : 200.00
258 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
259 CPU implementer : 0x43
260 CPU architecture: 8
261 CPU variant : 0x1
262 CPU part : 0x0a1
265 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderXT88ProcCpuInfo +
266 "CPU implementer : 0x43\n"
267 "CPU part : 0x0a1"),
268 "thunderxt88");
270 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderXT88ProcCpuInfo +
271 "CPU implementer : 0x43\n"
272 "CPU part : 0xa1"),
273 "thunderxt88");
275 // Verify HiSilicon processors.
276 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x48\n"
277 "CPU part : 0xd01"),
278 "tsv110");
280 // Verify A64FX.
281 const std::string A64FXProcCpuInfo = R"(
282 processor : 0
283 BogoMIPS : 200.00
284 Features : fp asimd evtstrm sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm fcma dcpop sve
285 CPU implementer : 0x46
286 CPU architecture: 8
287 CPU variant : 0x1
288 CPU part : 0x001
291 EXPECT_EQ(sys::detail::getHostCPUNameForARM(A64FXProcCpuInfo), "a64fx");
293 // Verify Nvidia Carmel.
294 const std::string CarmelProcCpuInfo = R"(
295 processor : 0
296 model name : ARMv8 Processor rev 0 (v8l)
297 BogoMIPS : 62.50
298 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm dcpop
299 CPU implementer : 0x4e
300 CPU architecture: 8
301 CPU variant : 0x0
302 CPU part : 0x004
303 CPU revision : 0
306 EXPECT_EQ(sys::detail::getHostCPUNameForARM(CarmelProcCpuInfo), "carmel");
308 // Snapdragon mixed implementer quirk
309 const std::string Snapdragon865ProcCPUInfo = R"(
310 processor : 0
311 BogoMIPS : 38.40
312 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
313 CPU implementer : 0x51
314 CPU architecture: 8
315 CPU variant : 0xd
316 CPU part : 0x805
317 CPU revision : 14
318 processor : 1
319 processor : 2
320 processor : 3
321 processor : 4
322 processor : 5
323 processor : 6
324 BogoMIPS : 38.40
325 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
326 CPU implementer : 0x41
327 CPU architecture: 8
328 CPU variant : 0x1
329 CPU part : 0xd0d
330 CPU revision : 0
332 EXPECT_EQ(sys::detail::getHostCPUNameForARM(Snapdragon865ProcCPUInfo), "cortex-a77");
335 TEST(getLinuxHostCPUName, s390x) {
336 SmallVector<std::string> ModelIDs(
337 {"3931", "8561", "3906", "2964", "2827", "2817", "2097", "2064"});
338 SmallVector<std::string> VectorSupport({"", "vx"});
339 SmallVector<StringRef> ExpectedCPUs;
341 // Model Id: 3931
342 ExpectedCPUs.push_back("zEC12");
343 ExpectedCPUs.push_back("z16");
345 // Model Id: 8561
346 ExpectedCPUs.push_back("zEC12");
347 ExpectedCPUs.push_back("z15");
349 // Model Id: 3906
350 ExpectedCPUs.push_back("zEC12");
351 ExpectedCPUs.push_back("z14");
353 // Model Id: 2964
354 ExpectedCPUs.push_back("zEC12");
355 ExpectedCPUs.push_back("z13");
357 // Model Id: 2827
358 ExpectedCPUs.push_back("zEC12");
359 ExpectedCPUs.push_back("zEC12");
361 // Model Id: 2817
362 ExpectedCPUs.push_back("z196");
363 ExpectedCPUs.push_back("z196");
365 // Model Id: 2097
366 ExpectedCPUs.push_back("z10");
367 ExpectedCPUs.push_back("z10");
369 // Model Id: 2064
370 ExpectedCPUs.push_back("generic");
371 ExpectedCPUs.push_back("generic");
373 const std::string DummyBaseVectorInfo =
374 "features : esan3 zarch stfle msa ldisp eimm dfp edat etf3eh highgprs "
375 "te ";
376 const std::string DummyBaseMachineInfo =
377 "processor 0: version = FF, identification = 059C88, machine = ";
379 int CheckIndex = 0;
380 for (size_t I = 0; I < ModelIDs.size(); I++) {
381 for (size_t J = 0; J < VectorSupport.size(); J++) {
382 const std::string DummyCPUInfo = DummyBaseVectorInfo + VectorSupport[J] +
383 "\n" + DummyBaseMachineInfo +
384 ModelIDs[I];
385 EXPECT_EQ(sys::detail::getHostCPUNameForS390x(DummyCPUInfo),
386 ExpectedCPUs[CheckIndex++]);
391 TEST(getLinuxHostCPUName, RISCV) {
392 const StringRef SifiveU74MCProcCPUInfo = R"(
393 processor : 0
394 hart : 2
395 isa : rv64imafdc
396 mmu : sv39
397 uarch : sifive,u74-mc
399 EXPECT_EQ(sys::detail::getHostCPUNameForRISCV(SifiveU74MCProcCPUInfo),
400 "sifive-u74");
401 EXPECT_EQ(
402 sys::detail::getHostCPUNameForRISCV("uarch : sifive,bullet0\n"),
403 "sifive-u74");
406 static bool runAndGetCommandOutput(
407 const char *ExePath, ArrayRef<llvm::StringRef> argv,
408 std::unique_ptr<char[]> &Buffer, off_t &Size) {
409 bool Success = false;
410 [ExePath, argv, &Buffer, &Size, &Success] {
411 using namespace llvm::sys;
412 SmallString<128> TestDirectory;
413 ASSERT_NO_ERROR(fs::createUniqueDirectory("host_test", TestDirectory));
415 SmallString<128> OutputFile(TestDirectory);
416 path::append(OutputFile, "out");
417 StringRef OutputPath = OutputFile.str();
419 const std::optional<StringRef> Redirects[] = {
420 /*STDIN=*/std::nullopt, /*STDOUT=*/OutputPath, /*STDERR=*/std::nullopt};
421 int RetCode =
422 ExecuteAndWait(ExePath, argv, /*env=*/std::nullopt, Redirects);
423 ASSERT_EQ(0, RetCode);
425 int FD = 0;
426 ASSERT_NO_ERROR(fs::openFileForRead(OutputPath, FD));
427 Size = ::lseek(FD, 0, SEEK_END);
428 ASSERT_NE(-1, Size);
429 ::lseek(FD, 0, SEEK_SET);
430 Buffer = std::make_unique<char[]>(Size);
431 ASSERT_EQ(::read(FD, Buffer.get(), Size), Size);
432 ::close(FD);
434 ASSERT_NO_ERROR(fs::remove(OutputPath));
435 ASSERT_NO_ERROR(fs::remove(TestDirectory.str()));
436 Success = true;
437 }();
438 return Success;
441 TEST(HostTest, DummyRunAndGetCommandOutputUse) {
442 // Suppress defined-but-not-used warnings when the tests using the helper are
443 // disabled.
444 (void)&runAndGetCommandOutput;
447 TEST(HostTest, getMacOSHostVersion) {
448 llvm::Triple HostTriple(llvm::sys::getProcessTriple());
449 if (!HostTriple.isMacOSX())
450 GTEST_SKIP();
452 const char *SwVersPath = "/usr/bin/sw_vers";
453 StringRef argv[] = {SwVersPath, "-productVersion"};
454 std::unique_ptr<char[]> Buffer;
455 off_t Size;
456 ASSERT_EQ(runAndGetCommandOutput(SwVersPath, argv, Buffer, Size), true);
457 StringRef SystemVersionStr = StringRef(Buffer.get(), Size).rtrim();
459 // Ensure that the two versions match.
460 VersionTuple SystemVersion;
461 ASSERT_EQ(llvm::Triple((Twine("x86_64-apple-macos") + SystemVersionStr))
462 .getMacOSXVersion(SystemVersion),
463 true);
464 VersionTuple HostVersion;
465 ASSERT_EQ(HostTriple.getMacOSXVersion(HostVersion), true);
467 if (SystemVersion.getMajor() > 10) {
468 // Don't compare the 'Minor' and 'Micro' versions, as they're always '0' for
469 // the 'Darwin' triples on 11.x.
470 ASSERT_EQ(SystemVersion.getMajor(), HostVersion.getMajor());
471 } else {
472 // Don't compare the 'Micro' version, as it's always '0' for the 'Darwin'
473 // triples.
474 ASSERT_EQ(SystemVersion.getMajor(), HostVersion.getMajor());
475 ASSERT_EQ(SystemVersion.getMinor(), HostVersion.getMinor());
479 // Helper to return AIX system version. Must return void to use ASSERT_*.
480 static void getAIXSystemVersion(VersionTuple &SystemVersion) {
481 const char *ExePath = "/usr/bin/oslevel";
482 StringRef argv[] = {ExePath};
483 std::unique_ptr<char[]> Buffer;
484 off_t Size;
485 ASSERT_EQ(runAndGetCommandOutput(ExePath, argv, Buffer, Size), true);
486 StringRef SystemVersionStr = StringRef(Buffer.get(), Size).rtrim();
488 SystemVersion =
489 llvm::Triple((Twine("powerpc-ibm-aix") + SystemVersionStr))
490 .getOSVersion();
493 TEST(HostTest, AIXHostVersionDetect) {
494 llvm::Triple HostTriple(llvm::sys::getProcessTriple());
495 if (HostTriple.getOS() != Triple::AIX)
496 GTEST_SKIP();
498 llvm::Triple ConfiguredHostTriple(LLVM_HOST_TRIPLE);
499 ASSERT_EQ(ConfiguredHostTriple.getOS(), Triple::AIX);
501 VersionTuple SystemVersion;
502 getAIXSystemVersion(SystemVersion);
504 // Ensure that the host triple version (major) and release (minor) numbers,
505 // unless explicitly configured, match with those of the current system.
506 auto SysMajor = SystemVersion.getMajor();
507 auto SysMinor = SystemVersion.getMinor();
508 VersionTuple HostVersion = HostTriple.getOSVersion();
509 if (ConfiguredHostTriple.getOSMajorVersion()) {
510 // Explicitly configured, force a match. We do it this way so the
511 // asserts are always executed.
512 SysMajor = HostVersion.getMajor();
513 SysMinor = HostVersion.getMinor();
515 ASSERT_EQ(SysMajor, HostVersion.getMajor());
516 ASSERT_EQ(SysMinor, HostVersion.getMinor());
519 TEST(HostTest, AIXTargetVersionDetect) {
520 llvm::Triple TargetTriple(llvm::sys::getDefaultTargetTriple());
521 if (TargetTriple.getOS() != Triple::AIX)
522 GTEST_SKIP();
524 // Ensure that the target triple version (major) and release (minor) numbers
525 // match with those of the current system.
526 llvm::Triple ConfiguredTargetTriple(LLVM_DEFAULT_TARGET_TRIPLE);
527 if (ConfiguredTargetTriple.getOSMajorVersion())
528 GTEST_SKIP(); // The version was configured explicitly; skip.
530 VersionTuple SystemVersion;
531 getAIXSystemVersion(SystemVersion);
532 VersionTuple TargetVersion = TargetTriple.getOSVersion();
533 ASSERT_EQ(SystemVersion.getMajor(), TargetVersion.getMajor());
534 ASSERT_EQ(SystemVersion.getMinor(), TargetVersion.getMinor());
537 TEST(HostTest, AIXHostCPUDetect) {
538 llvm::Triple HostTriple(llvm::sys::getProcessTriple());
539 if (HostTriple.getOS() != Triple::AIX)
540 GTEST_SKIP();
542 // Return a value based on the current processor implementation mode.
543 const char *ExePath = "/usr/sbin/getsystype";
544 StringRef argv[] = {ExePath, "-i"};
545 std::unique_ptr<char[]> Buffer;
546 off_t Size;
547 ASSERT_EQ(runAndGetCommandOutput(ExePath, argv, Buffer, Size), true);
548 StringRef CPU(Buffer.get(), Size);
549 StringRef MCPU = StringSwitch<const char *>(CPU)
550 .Case("POWER 4\n", "pwr4")
551 .Case("POWER 5\n", "pwr5")
552 .Case("POWER 6\n", "pwr6")
553 .Case("POWER 7\n", "pwr7")
554 .Case("POWER 8\n", "pwr8")
555 .Case("POWER 9\n", "pwr9")
556 .Case("POWER 10\n", "pwr10")
557 .Case("POWER 11\n", "pwr11")
558 .Default("unknown");
560 StringRef HostCPU = sys::getHostCPUName();
562 // Just do the comparison on the base implementation mode.
563 if (HostCPU == "970")
564 HostCPU = StringRef("pwr4");
565 else
566 HostCPU = HostCPU.rtrim('x');
568 EXPECT_EQ(HostCPU, MCPU);