Recommit "[TargetVersion] Only enable on RISC-V and AArch64" (#117110)" (#117128)
[llvm-project.git] / polly / test / CodeGen / non-affine-update___%bb1---%bb15.jscop
blob72a24adb456011edf01243b8a1c443faeecdebb7
2    "context" : "{  :  }",
3    "name" : "bb1 => bb15",
4    "statements" : [
5       {
6          "accesses" : [
7             {
8                "kind" : "read",
9                "relation" : "{ Stmt_bb2__TO__bb13[i0] -> MemRef_A[i0] }"
10             },
11             {
12                "kind" : "read",
13                "relation" : "{ Stmt_bb2__TO__bb13[i0] -> MemRef_C[42] }"
14             },
15             {
16                "kind" : "write",
17                "relation" : "{ Stmt_bb2__TO__bb13[i0] -> MemRef_C[42] }"
18             },
19             {
20                "kind" : "read",
21                "relation" : "{ Stmt_bb2__TO__bb13[i0] -> MemRef_B[113] }"
22             },
23             {
24                "kind" : "write",
25                "relation" : "{ Stmt_bb2__TO__bb13[i0] -> MemRef_B[113] }"
26             }
27          ],
28          "domain" : "{ Stmt_bb2__TO__bb13[i0] : i0 <= 9 and i0 >= 0 }",
29          "name" : "Stmt_bb2__TO__bb13",
30          "schedule" : "{ Stmt_bb2__TO__bb13[i0] -> [i0] }"
31       }
32    ]