llvm/lib/CodeGen/MachineRegisterInfo.cpp

   1 //===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // Implementation of the MachineRegisterInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "llvm/CodeGen/MachineRegisterInfo.h"
  14 #include "llvm/ADT/iterator_range.h"
  15 #include "llvm/CodeGen/MachineBasicBlock.h"
  16 #include "llvm/CodeGen/MachineFunction.h"
  17 #include "llvm/CodeGen/MachineInstr.h"
  18 #include "llvm/CodeGen/MachineInstrBuilder.h"
  19 #include "llvm/CodeGen/MachineOperand.h"
  20 #include "llvm/CodeGen/TargetInstrInfo.h"
  21 #include "llvm/CodeGen/TargetRegisterInfo.h"
  22 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  23 #include "llvm/Config/llvm-config.h"
  24 #include "llvm/IR/Attributes.h"
  25 #include "llvm/IR/DebugLoc.h"
  26 #include "llvm/IR/Function.h"
  27 #include "llvm/MC/MCRegisterInfo.h"
  28 #include "llvm/Support/Casting.h"
  29 #include "llvm/Support/CommandLine.h"
  30 #include "llvm/Support/Compiler.h"
  31 #include "llvm/Support/ErrorHandling.h"
  32 #include "llvm/Support/raw_ostream.h"
  33 #include <cassert>
  34
  35 using namespace llvm;
  36
  37 static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
  38   cl::init(true), cl::desc("Enable subregister liveness tracking."));
  39
  40 // Pin the vtable to this file.
  41 void MachineRegisterInfo::Delegate::anchor() {}
  42
  43 MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
  44     : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
  45                                    EnableSubRegLiveness) {
  46   unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
  47   VRegInfo.reserve(256);
  48   RegAllocHints.reserve(256);
  49   UsedPhysRegMask.resize(NumRegs);
  50   PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
  51   TheDelegates.clear();
  52 }
  53
  54 /// setRegClass - Set the register class of the specified virtual register.
  55 ///
  56 void
  57 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) {
  58   assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
  59   VRegInfo[Reg].first = RC;
  60 }
  61
  62 void MachineRegisterInfo::setRegBank(Register Reg,
  63                                      const RegisterBank &RegBank) {
  64   VRegInfo[Reg].first = &RegBank;
  65 }
  66
  67 static const TargetRegisterClass *
  68 constrainRegClass(MachineRegisterInfo &MRI, Register Reg,
  69                   const TargetRegisterClass *OldRC,
  70                   const TargetRegisterClass *RC, unsigned MinNumRegs) {
  71   if (OldRC == RC)
  72     return RC;
  73   const TargetRegisterClass *NewRC =
  74       MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
  75   if (!NewRC || NewRC == OldRC)
  76     return NewRC;
  77   if (NewRC->getNumRegs() < MinNumRegs)
  78     return nullptr;
  79   MRI.setRegClass(Reg, NewRC);
  80   return NewRC;
  81 }
  82
  83 const TargetRegisterClass *MachineRegisterInfo::constrainRegClass(
  84     Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) {
  85   if (Reg.isPhysical())
  86     return nullptr;
  87   return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
  88 }
  89
  90 bool
  91 MachineRegisterInfo::constrainRegAttrs(Register Reg,
  92                                        Register ConstrainingReg,
  93                                        unsigned MinNumRegs) {
  94   const LLT RegTy = getType(Reg);
  95   const LLT ConstrainingRegTy = getType(ConstrainingReg);
  96   if (RegTy.isValid() && ConstrainingRegTy.isValid() &&
  97       RegTy != ConstrainingRegTy)
  98     return false;
  99   const auto &ConstrainingRegCB = getRegClassOrRegBank(ConstrainingReg);
 100   if (!ConstrainingRegCB.isNull()) {
 101     const auto &RegCB = getRegClassOrRegBank(Reg);
 102     if (RegCB.isNull())
 103       setRegClassOrRegBank(Reg, ConstrainingRegCB);
 104     else if (isa<const TargetRegisterClass *>(RegCB) !=
 105              isa<const TargetRegisterClass *>(ConstrainingRegCB))
 106       return false;
 107     else if (isa<const TargetRegisterClass *>(RegCB)) {
 108       if (!::constrainRegClass(
 109               *this, Reg, cast<const TargetRegisterClass *>(RegCB),
 110               cast<const TargetRegisterClass *>(ConstrainingRegCB), MinNumRegs))
 111         return false;
 112     } else if (RegCB != ConstrainingRegCB)
 113       return false;
 114   }
 115   if (ConstrainingRegTy.isValid())
 116     setType(Reg, ConstrainingRegTy);
 117   return true;
 118 }
 119
 120 bool
 121 MachineRegisterInfo::recomputeRegClass(Register Reg) {
 122   const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
 123   const TargetRegisterClass *OldRC = getRegClass(Reg);
 124   const TargetRegisterClass *NewRC =
 125       getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC, *MF);
 126
 127   // Stop early if there is no room to grow.
 128   if (NewRC == OldRC)
 129     return false;
 130
 131   // Accumulate constraints from all uses.
 132   for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
 133     // Apply the effect of the given operand to NewRC.
 134     MachineInstr *MI = MO.getParent();
 135     unsigned OpNo = &MO - &MI->getOperand(0);
 136     NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
 137                                             getTargetRegisterInfo());
 138     if (!NewRC || NewRC == OldRC)
 139       return false;
 140   }
 141   setRegClass(Reg, NewRC);
 142   return true;
 143 }
 144
 145 Register MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) {
 146   Register Reg = Register::index2VirtReg(getNumVirtRegs());
 147   VRegInfo.grow(Reg);
 148   RegAllocHints.grow(Reg);
 149   insertVRegByName(Name, Reg);
 150   return Reg;
 151 }
 152
 153 /// createVirtualRegister - Create and return a new virtual register in the
 154 /// function with the specified register class.
 155 ///
 156 Register
 157 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass,
 158                                            StringRef Name) {
 159   assert(RegClass && "Cannot create register without RegClass!");
 160   assert(RegClass->isAllocatable() &&
 161          "Virtual register RegClass must be allocatable.");
 162
 163   // New virtual register number.
 164   Register Reg = createIncompleteVirtualRegister(Name);
 165   VRegInfo[Reg].first = RegClass;
 166   noteNewVirtualRegister(Reg);
 167   return Reg;
 168 }
 169
 170 Register MachineRegisterInfo::cloneVirtualRegister(Register VReg,
 171                                                    StringRef Name) {
 172   Register Reg = createIncompleteVirtualRegister(Name);
 173   VRegInfo[Reg].first = VRegInfo[VReg].first;
 174   setType(Reg, getType(VReg));
 175   noteCloneVirtualRegister(Reg, VReg);
 176   return Reg;
 177 }
 178
 179 void MachineRegisterInfo::setType(Register VReg, LLT Ty) {
 180   VRegToType.grow(VReg);
 181   VRegToType[VReg] = Ty;
 182 }
 183
 184 Register
 185 MachineRegisterInfo::createGenericVirtualRegister(LLT Ty, StringRef Name) {
 186   // New virtual register number.
 187   Register Reg = createIncompleteVirtualRegister(Name);
 188   // FIXME: Should we use a dummy register class?
 189   VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
 190   setType(Reg, Ty);
 191   noteNewVirtualRegister(Reg);
 192   return Reg;
 193 }
 194
 195 void MachineRegisterInfo::clearVirtRegTypes() { VRegToType.clear(); }
 196
 197 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
 198 void MachineRegisterInfo::clearVirtRegs() {
 199 #ifndef NDEBUG
 200   for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
 201     Register Reg = Register::index2VirtReg(i);
 202     if (!VRegInfo[Reg].second)
 203       continue;
 204     verifyUseList(Reg);
 205     errs() << "Remaining virtual register "
 206            << printReg(Reg, getTargetRegisterInfo()) << "...\n";
 207     for (MachineInstr &MI : reg_instructions(Reg))
 208       errs() << "...in instruction: " << MI << "\n";
 209     std::abort();
 210   }
 211 #endif
 212   VRegInfo.clear();
 213   for (auto &I : LiveIns)
 214     I.second = 0;
 215 }
 216
 217 void MachineRegisterInfo::verifyUseList(Register Reg) const {
 218 #ifndef NDEBUG
 219   bool Valid = true;
 220   for (MachineOperand &M : reg_operands(Reg)) {
 221     MachineOperand *MO = &M;
 222     MachineInstr *MI = MO->getParent();
 223     if (!MI) {
 224       errs() << printReg(Reg, getTargetRegisterInfo())
 225              << " use list MachineOperand " << MO
 226              << " has no parent instruction.\n";
 227       Valid = false;
 228       continue;
 229     }
 230     MachineOperand *MO0 = &MI->getOperand(0);
 231     unsigned NumOps = MI->getNumOperands();
 232     if (!(MO >= MO0 && MO < MO0+NumOps)) {
 233       errs() << printReg(Reg, getTargetRegisterInfo())
 234              << " use list MachineOperand " << MO
 235              << " doesn't belong to parent MI: " << *MI;
 236       Valid = false;
 237     }
 238     if (!MO->isReg()) {
 239       errs() << printReg(Reg, getTargetRegisterInfo())
 240              << " MachineOperand " << MO << ": " << *MO
 241              << " is not a register\n";
 242       Valid = false;
 243     }
 244     if (MO->getReg() != Reg) {
 245       errs() << printReg(Reg, getTargetRegisterInfo())
 246              << " use-list MachineOperand " << MO << ": "
 247              << *MO << " is the wrong register\n";
 248       Valid = false;
 249     }
 250   }
 251   assert(Valid && "Invalid use list");
 252 #endif
 253 }
 254
 255 void MachineRegisterInfo::verifyUseLists() const {
 256 #ifndef NDEBUG
 257   for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
 258     verifyUseList(Register::index2VirtReg(i));
 259   for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
 260     verifyUseList(i);
 261 #endif
 262 }
 263
 264 /// Add MO to the linked list of operands for its register.
 265 void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
 266   assert(!MO->isOnRegUseList() && "Already on list");
 267   MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
 268   MachineOperand *const Head = HeadRef;
 269
 270   // Head points to the first list element.
 271   // Next is NULL on the last list element.
 272   // Prev pointers are circular, so Head->Prev == Last.
 273
 274   // Head is NULL for an empty list.
 275   if (!Head) {
 276     MO->Contents.Reg.Prev = MO;
 277     MO->Contents.Reg.Next = nullptr;
 278     HeadRef = MO;
 279     return;
 280   }
 281   assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
 282
 283   // Insert MO between Last and Head in the circular Prev chain.
 284   MachineOperand *Last = Head->Contents.Reg.Prev;
 285   assert(Last && "Inconsistent use list");
 286   assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
 287   Head->Contents.Reg.Prev = MO;
 288   MO->Contents.Reg.Prev = Last;
 289
 290   // Def operands always precede uses. This allows def_iterator to stop early.
 291   // Insert def operands at the front, and use operands at the back.
 292   if (MO->isDef()) {
 293     // Insert def at the front.
 294     MO->Contents.Reg.Next = Head;
 295     HeadRef = MO;
 296   } else {
 297     // Insert use at the end.
 298     MO->Contents.Reg.Next = nullptr;
 299     Last->Contents.Reg.Next = MO;
 300   }
 301 }
 302
 303 /// Remove MO from its use-def list.
 304 void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
 305   assert(MO->isOnRegUseList() && "Operand not on use list");
 306   MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
 307   MachineOperand *const Head = HeadRef;
 308   assert(Head && "List already empty");
 309
 310   // Unlink this from the doubly linked list of operands.
 311   MachineOperand *Next = MO->Contents.Reg.Next;
 312   MachineOperand *Prev = MO->Contents.Reg.Prev;
 313
 314   // Prev links are circular, next link is NULL instead of looping back to Head.
 315   if (MO == Head)
 316     HeadRef = Next;
 317   else
 318     Prev->Contents.Reg.Next = Next;
 319
 320   (Next ? Next : Head)->Contents.Reg.Prev = Prev;
 321
 322   MO->Contents.Reg.Prev = nullptr;
 323   MO->Contents.Reg.Next = nullptr;
 324 }
 325
 326 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
 327 ///
 328 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
 329 /// operands that won't be destroyed, which is OK because the MO destructor is
 330 /// trivial anyway).
 331 ///
 332 /// The Src and Dst ranges may overlap.
 333 void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
 334                                        MachineOperand *Src,
 335                                        unsigned NumOps) {
 336   assert(Src != Dst && NumOps && "Noop moveOperands");
 337
 338   // Copy backwards if Dst is within the Src range.
 339   int Stride = 1;
 340   if (Dst >= Src && Dst < Src + NumOps) {
 341     Stride = -1;
 342     Dst += NumOps - 1;
 343     Src += NumOps - 1;
 344   }
 345
 346   // Copy one operand at a time.
 347   do {
 348     new (Dst) MachineOperand(*Src);
 349
 350     // Dst takes Src's place in the use-def chain.
 351     if (Src->isReg()) {
 352       MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
 353       MachineOperand *Prev = Src->Contents.Reg.Prev;
 354       MachineOperand *Next = Src->Contents.Reg.Next;
 355       assert(Head && "List empty, but operand is chained");
 356       assert(Prev && "Operand was not on use-def list");
 357
 358       // Prev links are circular, next link is NULL instead of looping back to
 359       // Head.
 360       if (Src == Head)
 361         Head = Dst;
 362       else
 363         Prev->Contents.Reg.Next = Dst;
 364
 365       // Update Prev pointer. This also works when Src was pointing to itself
 366       // in a 1-element list. In that case Head == Dst.
 367       (Next ? Next : Head)->Contents.Reg.Prev = Dst;
 368     }
 369
 370     Dst += Stride;
 371     Src += Stride;
 372   } while (--NumOps);
 373 }
 374
 375 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
 376 /// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
 377 /// except that it also changes any definitions of the register as well.
 378 /// If ToReg is a physical register we apply the sub register to obtain the
 379 /// final/proper physical register.
 380 void MachineRegisterInfo::replaceRegWith(Register FromReg, Register ToReg) {
 381   assert(FromReg != ToReg && "Cannot replace a reg with itself");
 382
 383   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 384
 385   // TODO: This could be more efficient by bulk changing the operands.
 386   for (MachineOperand &O : llvm::make_early_inc_range(reg_operands(FromReg))) {
 387     if (ToReg.isPhysical()) {
 388       O.substPhysReg(ToReg, *TRI);
 389     } else {
 390       O.setReg(ToReg);
 391     }
 392   }
 393 }
 394
 395 /// getVRegDef - Return the machine instr that defines the specified virtual
 396 /// register or null if none is found.  This assumes that the code is in SSA
 397 /// form, so there should only be one definition.
 398 MachineInstr *MachineRegisterInfo::getVRegDef(Register Reg) const {
 399   // Since we are in SSA form, we can use the first definition.
 400   def_instr_iterator I = def_instr_begin(Reg);
 401   assert((I.atEnd() || std::next(I) == def_instr_end()) &&
 402          "getVRegDef assumes a single definition or no definition");
 403   return !I.atEnd() ? &*I : nullptr;
 404 }
 405
 406 /// getUniqueVRegDef - Return the unique machine instr that defines the
 407 /// specified virtual register or null if none is found.  If there are
 408 /// multiple definitions or no definition, return null.
 409 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(Register Reg) const {
 410   if (def_empty(Reg)) return nullptr;
 411   def_instr_iterator I = def_instr_begin(Reg);
 412   if (std::next(I) != def_instr_end())
 413     return nullptr;
 414   return &*I;
 415 }
 416
 417 bool MachineRegisterInfo::hasOneNonDBGUse(Register RegNo) const {
 418   return hasSingleElement(use_nodbg_operands(RegNo));
 419 }
 420
 421 bool MachineRegisterInfo::hasOneNonDBGUser(Register RegNo) const {
 422   return hasSingleElement(use_nodbg_instructions(RegNo));
 423 }
 424
 425 bool MachineRegisterInfo::hasAtMostUserInstrs(Register Reg,
 426                                               unsigned MaxUsers) const {
 427   return hasNItemsOrLess(use_instr_nodbg_begin(Reg), use_instr_nodbg_end(),
 428                          MaxUsers);
 429 }
 430
 431 /// clearKillFlags - Iterate over all the uses of the given register and
 432 /// clear the kill flag from the MachineOperand. This function is used by
 433 /// optimization passes which extend register lifetimes and need only
 434 /// preserve conservative kill flag information.
 435 void MachineRegisterInfo::clearKillFlags(Register Reg) const {
 436   for (MachineOperand &MO : use_operands(Reg))
 437     MO.setIsKill(false);
 438 }
 439
 440 bool MachineRegisterInfo::isLiveIn(Register Reg) const {
 441   for (const std::pair<MCRegister, Register> &LI : liveins())
 442     if ((Register)LI.first == Reg || LI.second == Reg)
 443       return true;
 444   return false;
 445 }
 446
 447 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
 448 /// corresponding live-in physical register.
 449 MCRegister MachineRegisterInfo::getLiveInPhysReg(Register VReg) const {
 450   for (const std::pair<MCRegister, Register> &LI : liveins())
 451     if (LI.second == VReg)
 452       return LI.first;
 453   return MCRegister();
 454 }
 455
 456 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
 457 /// corresponding live-in physical register.
 458 Register MachineRegisterInfo::getLiveInVirtReg(MCRegister PReg) const {
 459   for (const std::pair<MCRegister, Register> &LI : liveins())
 460     if (LI.first == PReg)
 461       return LI.second;
 462   return Register();
 463 }
 464
 465 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
 466 /// into the given entry block.
 467 void
 468 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
 469                                       const TargetRegisterInfo &TRI,
 470                                       const TargetInstrInfo &TII) {
 471   // Emit the copies into the top of the block.
 472   for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
 473     if (LiveIns[i].second) {
 474       if (use_nodbg_empty(LiveIns[i].second)) {
 475         // The livein has no non-dbg uses. Drop it.
 476         //
 477         // It would be preferable to have isel avoid creating live-in
 478         // records for unused arguments in the first place, but it's
 479         // complicated by the debug info code for arguments.
 480         LiveIns.erase(LiveIns.begin() + i);
 481         --i; --e;
 482       } else {
 483         // Emit a copy.
 484         BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
 485                 TII.get(TargetOpcode::COPY), LiveIns[i].second)
 486           .addReg(LiveIns[i].first);
 487
 488         // Add the register to the entry block live-in set.
 489         EntryMBB->addLiveIn(LiveIns[i].first);
 490       }
 491     } else {
 492       // Add the register to the entry block live-in set.
 493       EntryMBB->addLiveIn(LiveIns[i].first);
 494     }
 495 }
 496
 497 LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(Register Reg) const {
 498   // Lane masks are only defined for vregs.
 499   assert(Reg.isVirtual());
 500   const TargetRegisterClass &TRC = *getRegClass(Reg);
 501   return TRC.getLaneMask();
 502 }
 503
 504 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 505 LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(Register Reg) const {
 506   for (MachineInstr &I : use_instructions(Reg))
 507     I.dump();
 508 }
 509 #endif
 510
 511 void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
 512   ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
 513   assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
 514          "Invalid ReservedRegs vector from target");
 515 }
 516
 517 bool MachineRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
 518   assert(Register::isPhysicalRegister(PhysReg));
 519
 520   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 521   if (TRI->isConstantPhysReg(PhysReg))
 522     return true;
 523
 524   // Check if any overlapping register is modified, or allocatable so it may be
 525   // used later.
 526   for (MCRegAliasIterator AI(PhysReg, TRI, true);
 527        AI.isValid(); ++AI)
 528     if (!def_empty(*AI) || isAllocatable(*AI))
 529       return false;
 530   return true;
 531 }
 532
 533 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
 534 /// specified register as undefined which causes the DBG_VALUE to be
 535 /// deleted during LiveDebugVariables analysis.
 536 void MachineRegisterInfo::markUsesInDebugValueAsUndef(Register Reg) const {
 537   // Mark any DBG_VALUE* that uses Reg as undef (but don't delete it.)
 538   // We use make_early_inc_range because setReg invalidates the iterator.
 539   for (MachineInstr &UseMI : llvm::make_early_inc_range(use_instructions(Reg))) {
 540     if (UseMI.isDebugValue() && UseMI.hasDebugOperandForReg(Reg))
 541       UseMI.setDebugValueUndef();
 542   }
 543 }
 544
 545 static const Function *getCalledFunction(const MachineInstr &MI) {
 546   for (const MachineOperand &MO : MI.operands()) {
 547     if (!MO.isGlobal())
 548       continue;
 549     const Function *Func = dyn_cast<Function>(MO.getGlobal());
 550     if (Func != nullptr)
 551       return Func;
 552   }
 553   return nullptr;
 554 }
 555
 556 static bool isNoReturnDef(const MachineOperand &MO) {
 557   // Anything which is not a noreturn function is a real def.
 558   const MachineInstr &MI = *MO.getParent();
 559   if (!MI.isCall())
 560     return false;
 561   const MachineBasicBlock &MBB = *MI.getParent();
 562   if (!MBB.succ_empty())
 563     return false;
 564   const MachineFunction &MF = *MBB.getParent();
 565   // We need to keep correct unwind information even if the function will
 566   // not return, since the runtime may need it.
 567   if (MF.getFunction().hasFnAttribute(Attribute::UWTable))
 568     return false;
 569   const Function *Called = getCalledFunction(MI);
 570   return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||
 571            !Called->hasFnAttribute(Attribute::NoUnwind));
 572 }
 573
 574 bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg,
 575                                             bool SkipNoReturnDef) const {
 576   if (UsedPhysRegMask.test(PhysReg))
 577     return true;
 578   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 579   for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
 580     for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
 581       if (!SkipNoReturnDef && isNoReturnDef(MO))
 582         continue;
 583       return true;
 584     }
 585   }
 586   return false;
 587 }
 588
 589 bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg,
 590                                         bool SkipRegMaskTest) const {
 591   if (!SkipRegMaskTest && UsedPhysRegMask.test(PhysReg))
 592     return true;
 593   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 594   for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
 595        ++AliasReg) {
 596     if (!reg_nodbg_empty(*AliasReg))
 597       return true;
 598   }
 599   return false;
 600 }
 601
 602 void MachineRegisterInfo::disableCalleeSavedRegister(MCRegister Reg) {
 603
 604   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 605   assert(Reg && (Reg < TRI->getNumRegs()) &&
 606          "Trying to disable an invalid register");
 607
 608   if (!IsUpdatedCSRsInitialized) {
 609     const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
 610     for (const MCPhysReg *I = CSR; *I; ++I)
 611       UpdatedCSRs.push_back(*I);
 612
 613     // Zero value represents the end of the register list
 614     // (no more registers should be pushed).
 615     UpdatedCSRs.push_back(0);
 616
 617     IsUpdatedCSRsInitialized = true;
 618   }
 619
 620   // Remove the register (and its aliases from the list).
 621   for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
 622     llvm::erase(UpdatedCSRs, *AI);
 623 }
 624
 625 const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const {
 626   if (IsUpdatedCSRsInitialized)
 627     return UpdatedCSRs.data();
 628
 629   return getTargetRegisterInfo()->getCalleeSavedRegs(MF);
 630 }
 631
 632 void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) {
 633   if (IsUpdatedCSRsInitialized)
 634     UpdatedCSRs.clear();
 635
 636   append_range(UpdatedCSRs, CSRs);
 637
 638   // Zero value represents the end of the register list
 639   // (no more registers should be pushed).
 640   UpdatedCSRs.push_back(0);
 641   IsUpdatedCSRsInitialized = true;
 642 }
 643
 644 bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
 645   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 646   for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
 647     if (all_of(TRI->superregs_inclusive(*Root),
 648                [&](MCPhysReg Super) { return isReserved(Super); }))
 649       return true;
 650   }
 651   return false;
 652 }
 653
 654 bool MachineRegisterInfo::isArgumentRegister(const MachineFunction &MF,
 655                                              MCRegister Reg) const {
 656   return getTargetRegisterInfo()->isArgumentRegister(MF, Reg);
 657 }
 658
 659 bool MachineRegisterInfo::isFixedRegister(const MachineFunction &MF,
 660                                           MCRegister Reg) const {
 661   return getTargetRegisterInfo()->isFixedRegister(MF, Reg);
 662 }
 663
 664 bool MachineRegisterInfo::isGeneralPurposeRegister(const MachineFunction &MF,
 665                                                    MCRegister Reg) const {
 666   return getTargetRegisterInfo()->isGeneralPurposeRegister(MF, Reg);
 667 }