llvm/lib/CodeGen/RegisterBank.cpp

   1 //===- llvm/CodeGen/GlobalISel/RegisterBank.cpp - Register Bank --*- C++ -*-==//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 /// This file implements the RegisterBank class.
  10 //===----------------------------------------------------------------------===//
  11
  12 #include "llvm/CodeGen/RegisterBank.h"
  13 #include "llvm/ADT/StringExtras.h"
  14 #include "llvm/CodeGen/RegisterBankInfo.h"
  15 #include "llvm/CodeGen/TargetRegisterInfo.h"
  16 #include "llvm/Config/llvm-config.h"
  17 #include "llvm/Support/Debug.h"
  18
  19 #define DEBUG_TYPE "registerbank"
  20
  21 using namespace llvm;
  22
  23 bool RegisterBank::verify(const RegisterBankInfo &RBI,
  24                           const TargetRegisterInfo &TRI) const {
  25   for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) {
  26     const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
  27
  28     if (!covers(RC))
  29       continue;
  30     // Verify that the register bank covers all the sub classes of the
  31     // classes it covers.
  32
  33     // Use a different (slow in that case) method than
  34     // RegisterBankInfo to find the subclasses of RC, to make sure
  35     // both agree on the covers.
  36     for (unsigned SubRCId = 0; SubRCId != End; ++SubRCId) {
  37       const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
  38
  39       if (!RC.hasSubClassEq(&SubRC))
  40         continue;
  41
  42       // Verify that the Size of the register bank is big enough to cover
  43       // all the register classes it covers.
  44       assert(RBI.getMaximumSize(getID()) >= TRI.getRegSizeInBits(SubRC) &&
  45              "Size is not big enough for all the subclasses!");
  46       assert(covers(SubRC) && "Not all subclasses are covered");
  47     }
  48   }
  49   return true;
  50 }
  51
  52 bool RegisterBank::covers(const TargetRegisterClass &RC) const {
  53   return (CoveredClasses[RC.getID() / 32] & (1U << RC.getID() % 32)) != 0;
  54 }
  55
  56 bool RegisterBank::operator==(const RegisterBank &OtherRB) const {
  57   // There must be only one instance of a given register bank alive
  58   // for the whole compilation.
  59   // The RegisterBankInfo is supposed to enforce that.
  60   assert((OtherRB.getID() != getID() || &OtherRB == this) &&
  61          "ID does not uniquely identify a RegisterBank");
  62   return &OtherRB == this;
  63 }
  64
  65 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
  66 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const {
  67   print(dbgs(), /* IsForDebug */ true, TRI);
  68 }
  69 #endif
  70
  71 void RegisterBank::print(raw_ostream &OS, bool IsForDebug,
  72                          const TargetRegisterInfo *TRI) const {
  73   OS << getName();
  74   if (!IsForDebug)
  75     return;
  76
  77   unsigned Count = 0;
  78   for (int i = 0, e = ((NumRegClasses + 31) / 32); i != e; ++i)
  79     Count += llvm::popcount(CoveredClasses[i]);
  80
  81   OS << "(ID:" << getID() << ")\n"
  82      << "Number of Covered register classes: " << Count << '\n';
  83   // Print all the subclasses if we can.
  84   // This register classes may not be properly initialized yet.
  85   if (!TRI || NumRegClasses == 0)
  86     return;
  87   assert(NumRegClasses == TRI->getNumRegClasses() &&
  88          "TRI does not match the initialization process?");
  89   OS << "Covered register classes:\n";
  90   ListSeparator LS;
  91   for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) {
  92     const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
  93
  94     if (covers(RC))
  95       OS << LS << TRI->getRegClassName(&RC);
  96   }
  97 }