1 //===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 /// \file This file describes the general parts of a Subtarget.
11 //===----------------------------------------------------------------------===//
13 #include "llvm/CodeGen/TargetSubtargetInfo.h"
17 TargetSubtargetInfo::TargetSubtargetInfo(
18 const Triple
&TT
, StringRef CPU
, StringRef TuneCPU
, StringRef FS
,
19 ArrayRef
<SubtargetFeatureKV
> PF
, ArrayRef
<SubtargetSubTypeKV
> PD
,
20 const MCWriteProcResEntry
*WPR
, const MCWriteLatencyEntry
*WL
,
21 const MCReadAdvanceEntry
*RA
, const InstrStage
*IS
, const unsigned *OC
,
23 : MCSubtargetInfo(TT
, CPU
, TuneCPU
, FS
, PF
, PD
, WPR
, WL
, RA
, IS
, OC
, FP
) {}
25 TargetSubtargetInfo::~TargetSubtargetInfo() = default;
27 bool TargetSubtargetInfo::enableAtomicExpand() const {
31 bool TargetSubtargetInfo::enableIndirectBrExpand() const {
35 bool TargetSubtargetInfo::enableMachineScheduler() const {
39 bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
40 return enableMachineScheduler();
43 bool TargetSubtargetInfo::enableRALocalReassignment(
44 CodeGenOptLevel OptLevel
) const {
48 bool TargetSubtargetInfo::enablePostRAScheduler() const {
49 return getSchedModel().PostRAScheduler
;
52 bool TargetSubtargetInfo::enablePostRAMachineScheduler() const {
53 return enableMachineScheduler() && enablePostRAScheduler();
56 bool TargetSubtargetInfo::useAA() const {
60 void TargetSubtargetInfo::mirFileLoaded(MachineFunction
&MF
) const { }