[RISCV] Fix mgather -> riscv.masked.strided.load combine not extending indices (...
[llvm-project.git] / llvm / lib / MC / MCELFObjectTargetWriter.cpp
blobc35e1f26dc1efa07dc09968e145e8d63c73fc4a6
1 //===-- MCELFObjectTargetWriter.cpp - ELF Target Writer Subclass ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
9 #include "llvm/MC/MCELFObjectWriter.h"
11 using namespace llvm;
13 MCELFObjectTargetWriter::MCELFObjectTargetWriter(bool Is64Bit_, uint8_t OSABI_,
14 uint16_t EMachine_,
15 bool HasRelocationAddend_,
16 uint8_t ABIVersion_)
17 : OSABI(OSABI_), ABIVersion(ABIVersion_), EMachine(EMachine_),
18 HasRelocationAddend(HasRelocationAddend_), Is64Bit(Is64Bit_) {}
20 bool MCELFObjectTargetWriter::needsRelocateWithSymbol(const MCValue &,
21 const MCSymbol &,
22 unsigned Type) const {
23 return false;
26 void
27 MCELFObjectTargetWriter::sortRelocs(const MCAssembler &Asm,
28 std::vector<ELFRelocationEntry> &Relocs) {
31 void MCELFObjectTargetWriter::addTargetSectionFlags(MCContext &Ctx,
32 MCSectionELF &Sec) {}