[RISCV] Fix mgather -> riscv.masked.strided.load combine not extending indices (...
[llvm-project.git] / llvm / lib / MC / MCMachObjectTargetWriter.cpp
bloba57b8a7ac0ff39f0f03cc46cbdf603803e5f505a
1 //===- MCMachObjectTargetWriter.cpp - Mach-O Target Writer Subclass -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
9 #include "llvm/MC/MCMachObjectWriter.h"
11 using namespace llvm;
13 MCMachObjectTargetWriter::MCMachObjectTargetWriter(bool Is64Bit_,
14 uint32_t CPUType_,
15 uint32_t CPUSubtype_)
16 : Is64Bit(Is64Bit_), CPUType(CPUType_), CPUSubtype(CPUSubtype_) {}
18 MCMachObjectTargetWriter::~MCMachObjectTargetWriter() = default;