[RISCV] Fix mgather -> riscv.masked.strided.load combine not extending indices (...
[llvm-project.git] / llvm / lib / Target / RISCV / GISel / RISCVLegalizerInfo.h
blobf3ec6be167347e8b995cb957f58bdc30dd79f0e3
1 //===-- RISCVLegalizerInfo.h ------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the Machinelegalizer class for RISC-V.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVMACHINELEGALIZER_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVMACHINELEGALIZER_H
16 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
18 namespace llvm {
20 class GISelChangeObserver;
21 class MachineIRBuilder;
22 class RISCVSubtarget;
24 class RISCVLegalizerInfo : public LegalizerInfo {
25 const RISCVSubtarget &STI;
26 const unsigned XLen;
27 const LLT sXLen;
29 public:
30 RISCVLegalizerInfo(const RISCVSubtarget &ST);
32 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
33 LostDebugLocObserver &LocObserver) const override;
35 bool legalizeIntrinsic(LegalizerHelper &Helper,
36 MachineInstr &MI) const override;
38 private:
39 bool legalizeShlAshrLshr(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
40 GISelChangeObserver &Observer) const;
42 bool legalizeVAStart(MachineInstr &MI, MachineIRBuilder &MIRBuilder) const;
44 } // end namespace llvm
45 #endif