llvm/lib/Target/RISCV/RISCVMacroFusion.td

   1 //==----- RISCVMacroFusion.td - Macro Fusion Definitions -----*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 // ===---------------------------------------------------------------------===//
  10 // The following definitions describe the macro fusion predicators.
  11
  12 // Fuse LUI followed by ADDI or ADDIW:
  13 //   rd = imm[31:0] which decomposes to
  14 //   lui rd, imm[31:12]
  15 //   addi(w) rd, rd, imm[11:0]
  16 def TuneLUIADDIFusion
  17   : SimpleFusion<"lui-addi-fusion", "HasLUIADDIFusion",
  18                  "Enable LUI+ADDI macro fusion",
  19                  CheckOpcode<[LUI]>,
  20                  CheckOpcode<[ADDI, ADDIW]>>;
  21
  22 // Fuse AUIPC followed by ADDI:
  23 //   auipc rd, imm20
  24 //   addi rd, rd, imm12
  25 def TuneAUIPCADDIFusion
  26   : SimpleFusion<"auipc-addi-fusion", "HasAUIPCADDIFusion",
  27                  "Enable AUIPC+ADDI macrofusion",
  28                  CheckOpcode<[AUIPC]>,
  29                  CheckOpcode<[ADDI]>>;
  30
  31 // Fuse zero extension of halfword:
  32 //   slli rd, rs1, 48
  33 //   srli rd, rd, 48
  34 def TuneZExtHFusion
  35   : SimpleFusion<"zexth-fusion", "HasZExtHFusion",
  36                  "Enable SLLI+SRLI to be fused to zero extension of halfword",
  37                  CheckAll<[
  38                    CheckOpcode<[SLLI]>,
  39                    CheckIsImmOperand<2>,
  40                    CheckImmOperand<2, 48>
  41                  ]>,
  42                  CheckAll<[
  43                    CheckOpcode<[SRLI]>,
  44                    CheckIsImmOperand<2>,
  45                    CheckImmOperand<2, 48>
  46                  ]>>;
  47
  48 // Fuse zero extension of word:
  49 //   slli rd, rs1, 32
  50 //   srli rd, rd, 32
  51 def TuneZExtWFusion
  52   : SimpleFusion<"zextw-fusion", "HasZExtWFusion",
  53                  "Enable SLLI+SRLI to be fused to zero extension of word",
  54                  CheckAll<[
  55                    CheckOpcode<[SLLI]>,
  56                    CheckIsImmOperand<2>,
  57                    CheckImmOperand<2, 32>
  58                  ]>,
  59                  CheckAll<[
  60                    CheckOpcode<[SRLI]>,
  61                    CheckIsImmOperand<2>,
  62                    CheckImmOperand<2, 32>
  63                  ]>>;
  64
  65 // Fuse shifted zero extension of word:
  66 //   slli rd, rs1, 32
  67 //   srli rd, rd, x
  68 //   where 0 <= x < 32
  69 def TuneShiftedZExtWFusion
  70   : SimpleFusion<"shifted-zextw-fusion", "HasShiftedZExtWFusion",
  71                  "Enable SLLI+SRLI to be fused when computing (shifted) word zero extension",
  72                  CheckAll<[
  73                    CheckOpcode<[SLLI]>,
  74                    CheckIsImmOperand<2>,
  75                    CheckImmOperand<2, 32>
  76                  ]>,
  77                  CheckAll<[
  78                    CheckOpcode<[SRLI]>,
  79                    CheckIsImmOperand<2>,
  80                    CheckImmOperandRange<2, 0, 31>
  81                  ]>>;
  82
  83 // Fuse load with add:
  84 //   add rd, rs1, rs2
  85 //   ld rd, 0(rd)
  86 def TuneLDADDFusion
  87   : SimpleFusion<"ld-add-fusion", "HasLDADDFusion", "Enable LD+ADD macrofusion",
  88                  CheckOpcode<[ADD]>,
  89                  CheckAll<[
  90                    CheckOpcode<[LD]>,
  91                    CheckIsImmOperand<2>,
  92                    CheckImmOperand<2, 0>
  93                  ]>>;