1 //===-- RISCVRegisterInfo.td - RISC-V Register defs --------*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
10 // Declarations that describe the RISC-V register files
11 //===----------------------------------------------------------------------===//
13 let Namespace = "RISCV" in {
14 class RISCVReg<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
15 let HWEncoding{4-0} = Enc;
19 class RISCVRegWithSubRegs<bits<5> Enc, string n, list<Register> subregs,
20 list<string> alt = []>
21 : RegisterWithSubRegs<n, subregs> {
22 let HWEncoding{4-0} = Enc;
26 class RISCVReg16<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
27 let HWEncoding{4-0} = Enc;
31 def sub_16 : SubRegIndex<16>;
32 class RISCVReg32<RISCVReg16 subreg>
33 : RISCVRegWithSubRegs<subreg.HWEncoding{4-0}, subreg.AsmName, [subreg],
35 let SubRegIndices = [sub_16];
38 // Because RISCVReg64 register have AsmName and AltNames that alias with their
39 // 16/32-bit sub-register, RISCVAsmParser will need to coerce a register number
40 // from a RISCVReg16/RISCVReg32 to the equivalent RISCVReg64 when appropriate.
41 def sub_32 : SubRegIndex<32>;
42 class RISCVReg64<RISCVReg32 subreg>
43 : RISCVRegWithSubRegs<subreg.HWEncoding{4-0}, subreg.AsmName, [subreg],
45 let SubRegIndices = [sub_32];
48 let FallbackRegAltNameIndex = NoRegAltName in
49 def ABIRegAltName : RegAltNameIndex;
51 def sub_vrm4_0 : SubRegIndex<256>;
52 def sub_vrm4_1 : SubRegIndex<256, 256>;
53 def sub_vrm2_0 : SubRegIndex<128>;
54 def sub_vrm2_1 : SubRegIndex<128, 128>;
55 def sub_vrm2_2 : ComposedSubRegIndex<sub_vrm4_1, sub_vrm2_0>;
56 def sub_vrm2_3 : ComposedSubRegIndex<sub_vrm4_1, sub_vrm2_1>;
57 def sub_vrm1_0 : SubRegIndex<64>;
58 def sub_vrm1_1 : SubRegIndex<64, 64>;
59 def sub_vrm1_2 : ComposedSubRegIndex<sub_vrm2_1, sub_vrm1_0>;
60 def sub_vrm1_3 : ComposedSubRegIndex<sub_vrm2_1, sub_vrm1_1>;
61 def sub_vrm1_4 : ComposedSubRegIndex<sub_vrm2_2, sub_vrm1_0>;
62 def sub_vrm1_5 : ComposedSubRegIndex<sub_vrm2_2, sub_vrm1_1>;
63 def sub_vrm1_6 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_0>;
64 def sub_vrm1_7 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_1>;
66 // GPR sizes change with HwMode.
67 // FIXME: Support HwMode in SubRegIndex?
68 def sub_gpr_even : SubRegIndex<-1>;
69 def sub_gpr_odd : SubRegIndex<-1, -1>;
70 } // Namespace = "RISCV"
73 // CostPerUse is set higher for registers that may not be compressible as they
74 // are not part of GPRC, the most restrictive register class used by the
75 // compressed instruction set. This will influence the greedy register
76 // allocator to reduce the use of registers that can't be encoded in 16 bit
79 let RegAltNameIndices = [ABIRegAltName] in {
80 let isConstant = true in
81 def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
82 let CostPerUse = [0, 1] in {
83 def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>;
84 def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>;
85 def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>;
86 def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>;
87 def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>;
88 def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>;
89 def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>;
91 def X8 : RISCVReg<8, "x8", ["s0", "fp"]>, DwarfRegNum<[8]>;
92 def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>;
93 def X10 : RISCVReg<10,"x10", ["a0"]>, DwarfRegNum<[10]>;
94 def X11 : RISCVReg<11,"x11", ["a1"]>, DwarfRegNum<[11]>;
95 def X12 : RISCVReg<12,"x12", ["a2"]>, DwarfRegNum<[12]>;
96 def X13 : RISCVReg<13,"x13", ["a3"]>, DwarfRegNum<[13]>;
97 def X14 : RISCVReg<14,"x14", ["a4"]>, DwarfRegNum<[14]>;
98 def X15 : RISCVReg<15,"x15", ["a5"]>, DwarfRegNum<[15]>;
99 let CostPerUse = [0, 1] in {
100 def X16 : RISCVReg<16,"x16", ["a6"]>, DwarfRegNum<[16]>;
101 def X17 : RISCVReg<17,"x17", ["a7"]>, DwarfRegNum<[17]>;
102 def X18 : RISCVReg<18,"x18", ["s2"]>, DwarfRegNum<[18]>;
103 def X19 : RISCVReg<19,"x19", ["s3"]>, DwarfRegNum<[19]>;
104 def X20 : RISCVReg<20,"x20", ["s4"]>, DwarfRegNum<[20]>;
105 def X21 : RISCVReg<21,"x21", ["s5"]>, DwarfRegNum<[21]>;
106 def X22 : RISCVReg<22,"x22", ["s6"]>, DwarfRegNum<[22]>;
107 def X23 : RISCVReg<23,"x23", ["s7"]>, DwarfRegNum<[23]>;
108 def X24 : RISCVReg<24,"x24", ["s8"]>, DwarfRegNum<[24]>;
109 def X25 : RISCVReg<25,"x25", ["s9"]>, DwarfRegNum<[25]>;
110 def X26 : RISCVReg<26,"x26", ["s10"]>, DwarfRegNum<[26]>;
111 def X27 : RISCVReg<27,"x27", ["s11"]>, DwarfRegNum<[27]>;
112 def X28 : RISCVReg<28,"x28", ["t3"]>, DwarfRegNum<[28]>;
113 def X29 : RISCVReg<29,"x29", ["t4"]>, DwarfRegNum<[29]>;
114 def X30 : RISCVReg<30,"x30", ["t5"]>, DwarfRegNum<[30]>;
115 def X31 : RISCVReg<31,"x31", ["t6"]>, DwarfRegNum<[31]>;
119 def XLenVT : ValueTypeByHwMode<[RV32, RV64],
121 // Allow f64 in GPR for ZDINX on RV64.
122 def XLenFVT : ValueTypeByHwMode<[RV64],
124 def XLenPairFVT : ValueTypeByHwMode<[RV32],
126 def XLenRI : RegInfoByHwMode<
128 [RegInfo<32,32,32>, RegInfo<64,64,64>]>;
130 class GPRRegisterClass<dag regList>
131 : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, regList> {
132 let RegInfos = XLenRI;
135 // The order of registers represents the preferred allocation sequence.
136 // Registers are listed in the order caller-save, callee-save, specials.
137 def GPR : GPRRegisterClass<(add (sequence "X%u", 10, 17),
138 (sequence "X%u", 5, 7),
139 (sequence "X%u", 28, 31),
140 (sequence "X%u", 8, 9),
141 (sequence "X%u", 18, 27),
142 (sequence "X%u", 0, 4))>;
144 def GPRX0 : GPRRegisterClass<(add X0)>;
145 def GPRX1 : GPRRegisterClass<(add X1)>;
146 def GPRX5 : GPRRegisterClass<(add X5)>;
148 def GPRNoX0 : GPRRegisterClass<(sub GPR, X0)>;
150 def GPRNoX0X2 : GPRRegisterClass<(sub GPR, X0, X2)>;
152 // Don't use X1 or X5 for JALR since that is a hint to pop the return address
153 // stack on some microarchitectures. Also remove the reserved registers X0, X2,
154 // X3, and X4 as it reduces the number of register classes that get synthesized
156 def GPRJALR : GPRRegisterClass<(sub GPR, (sequence "X%u", 0, 5))>;
158 def GPRC : GPRRegisterClass<(add (sequence "X%u", 10, 15),
159 (sequence "X%u", 8, 9))>;
161 // For indirect tail calls, we can't use callee-saved registers, as they are
162 // restored to the saved value before the tail call, which would clobber a call
163 // address. We shouldn't use x5 since that is a hint for to pop the return
164 // address stack on some microarchitectures.
165 def GPRTC : GPRRegisterClass<(add (sequence "X%u", 6, 7),
166 (sequence "X%u", 10, 17),
167 (sequence "X%u", 28, 31))>;
169 def SP : GPRRegisterClass<(add X2)>;
171 // Saved Registers from s0 to s7, for C.MVA01S07 instruction in Zcmp extension
172 def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
173 (sequence "X%u", 18, 23))>;
175 def GPRX1X5 : GPRRegisterClass<(add X1, X5)>;
177 // Floating point registers
178 let RegAltNameIndices = [ABIRegAltName] in {
179 def F0_H : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>;
180 def F1_H : RISCVReg16<1, "f1", ["ft1"]>, DwarfRegNum<[33]>;
181 def F2_H : RISCVReg16<2, "f2", ["ft2"]>, DwarfRegNum<[34]>;
182 def F3_H : RISCVReg16<3, "f3", ["ft3"]>, DwarfRegNum<[35]>;
183 def F4_H : RISCVReg16<4, "f4", ["ft4"]>, DwarfRegNum<[36]>;
184 def F5_H : RISCVReg16<5, "f5", ["ft5"]>, DwarfRegNum<[37]>;
185 def F6_H : RISCVReg16<6, "f6", ["ft6"]>, DwarfRegNum<[38]>;
186 def F7_H : RISCVReg16<7, "f7", ["ft7"]>, DwarfRegNum<[39]>;
187 def F8_H : RISCVReg16<8, "f8", ["fs0"]>, DwarfRegNum<[40]>;
188 def F9_H : RISCVReg16<9, "f9", ["fs1"]>, DwarfRegNum<[41]>;
189 def F10_H : RISCVReg16<10,"f10", ["fa0"]>, DwarfRegNum<[42]>;
190 def F11_H : RISCVReg16<11,"f11", ["fa1"]>, DwarfRegNum<[43]>;
191 def F12_H : RISCVReg16<12,"f12", ["fa2"]>, DwarfRegNum<[44]>;
192 def F13_H : RISCVReg16<13,"f13", ["fa3"]>, DwarfRegNum<[45]>;
193 def F14_H : RISCVReg16<14,"f14", ["fa4"]>, DwarfRegNum<[46]>;
194 def F15_H : RISCVReg16<15,"f15", ["fa5"]>, DwarfRegNum<[47]>;
195 def F16_H : RISCVReg16<16,"f16", ["fa6"]>, DwarfRegNum<[48]>;
196 def F17_H : RISCVReg16<17,"f17", ["fa7"]>, DwarfRegNum<[49]>;
197 def F18_H : RISCVReg16<18,"f18", ["fs2"]>, DwarfRegNum<[50]>;
198 def F19_H : RISCVReg16<19,"f19", ["fs3"]>, DwarfRegNum<[51]>;
199 def F20_H : RISCVReg16<20,"f20", ["fs4"]>, DwarfRegNum<[52]>;
200 def F21_H : RISCVReg16<21,"f21", ["fs5"]>, DwarfRegNum<[53]>;
201 def F22_H : RISCVReg16<22,"f22", ["fs6"]>, DwarfRegNum<[54]>;
202 def F23_H : RISCVReg16<23,"f23", ["fs7"]>, DwarfRegNum<[55]>;
203 def F24_H : RISCVReg16<24,"f24", ["fs8"]>, DwarfRegNum<[56]>;
204 def F25_H : RISCVReg16<25,"f25", ["fs9"]>, DwarfRegNum<[57]>;
205 def F26_H : RISCVReg16<26,"f26", ["fs10"]>, DwarfRegNum<[58]>;
206 def F27_H : RISCVReg16<27,"f27", ["fs11"]>, DwarfRegNum<[59]>;
207 def F28_H : RISCVReg16<28,"f28", ["ft8"]>, DwarfRegNum<[60]>;
208 def F29_H : RISCVReg16<29,"f29", ["ft9"]>, DwarfRegNum<[61]>;
209 def F30_H : RISCVReg16<30,"f30", ["ft10"]>, DwarfRegNum<[62]>;
210 def F31_H : RISCVReg16<31,"f31", ["ft11"]>, DwarfRegNum<[63]>;
212 foreach Index = 0-31 in {
213 def F#Index#_F : RISCVReg32<!cast<RISCVReg16>("F"#Index#"_H")>,
214 DwarfRegNum<[!add(Index, 32)]>;
217 foreach Index = 0-31 in {
218 def F#Index#_D : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_F")>,
219 DwarfRegNum<[!add(Index, 32)]>;
223 // The order of registers represents the preferred allocation sequence,
224 // meaning caller-save regs are listed before callee-save.
225 // We start by allocating argument registers in reverse order since they are
227 def FPR16 : RegisterClass<"RISCV", [f16, bf16], 16, (add
228 (sequence "F%u_H", 15, 10), // fa5-fa0
229 (sequence "F%u_H", 0, 7), // ft0-f7
230 (sequence "F%u_H", 16, 17), // fa6-fa7
231 (sequence "F%u_H", 28, 31), // ft8-ft11
232 (sequence "F%u_H", 8, 9), // fs0-fs1
233 (sequence "F%u_H", 18, 27) // fs2-fs11
236 def FPR32 : RegisterClass<"RISCV", [f32], 32, (add
237 (sequence "F%u_F", 15, 10),
238 (sequence "F%u_F", 0, 7),
239 (sequence "F%u_F", 16, 17),
240 (sequence "F%u_F", 28, 31),
241 (sequence "F%u_F", 8, 9),
242 (sequence "F%u_F", 18, 27)
245 def FPR32C : RegisterClass<"RISCV", [f32], 32, (add
246 (sequence "F%u_F", 15, 10),
247 (sequence "F%u_F", 8, 9)
250 // The order of registers represents the preferred allocation sequence,
251 // meaning caller-save regs are listed before callee-save.
252 def FPR64 : RegisterClass<"RISCV", [f64], 64, (add
253 (sequence "F%u_D", 15, 10),
254 (sequence "F%u_D", 0, 7),
255 (sequence "F%u_D", 16, 17),
256 (sequence "F%u_D", 28, 31),
257 (sequence "F%u_D", 8, 9),
258 (sequence "F%u_D", 18, 27)
261 def FPR64C : RegisterClass<"RISCV", [f64], 64, (add
262 (sequence "F%u_D", 15, 10),
263 (sequence "F%u_D", 8, 9)
266 // Vector type mapping to LLVM types.
268 // The V vector extension requires that VLEN >= 128 and <= 65536.
269 // Additionally, the only supported ELEN values are 32 and 64,
270 // thus `vscale` can be defined as VLEN/64,
271 // allowing the same types with either ELEN value.
273 // MF8 MF4 MF2 M1 M2 M4 M8
274 // i64* N/A N/A N/A nxv1i64 nxv2i64 nxv4i64 nxv8i64
275 // i32 N/A N/A nxv1i32 nxv2i32 nxv4i32 nxv8i32 nxv16i32
276 // i16 N/A nxv1i16 nxv2i16 nxv4i16 nxv8i16 nxv16i16 nxv32i16
277 // i8 nxv1i8 nxv2i8 nxv4i8 nxv8i8 nxv16i8 nxv32i8 nxv64i8
278 // double* N/A N/A N/A nxv1f64 nxv2f64 nxv4f64 nxv8f64
279 // float N/A N/A nxv1f32 nxv2f32 nxv4f32 nxv8f32 nxv16f32
280 // half N/A nxv1f16 nxv2f16 nxv4f16 nxv8f16 nxv16f16 nxv32f16
283 defvar vint8mf8_t = nxv1i8;
284 defvar vint8mf4_t = nxv2i8;
285 defvar vint8mf2_t = nxv4i8;
286 defvar vint8m1_t = nxv8i8;
287 defvar vint8m2_t = nxv16i8;
288 defvar vint8m4_t = nxv32i8;
289 defvar vint8m8_t = nxv64i8;
291 defvar vint16mf4_t = nxv1i16;
292 defvar vint16mf2_t = nxv2i16;
293 defvar vint16m1_t = nxv4i16;
294 defvar vint16m2_t = nxv8i16;
295 defvar vint16m4_t = nxv16i16;
296 defvar vint16m8_t = nxv32i16;
298 defvar vint32mf2_t = nxv1i32;
299 defvar vint32m1_t = nxv2i32;
300 defvar vint32m2_t = nxv4i32;
301 defvar vint32m4_t = nxv8i32;
302 defvar vint32m8_t = nxv16i32;
304 defvar vint64m1_t = nxv1i64;
305 defvar vint64m2_t = nxv2i64;
306 defvar vint64m4_t = nxv4i64;
307 defvar vint64m8_t = nxv8i64;
309 defvar vfloat16mf4_t = nxv1f16;
310 defvar vfloat16mf2_t = nxv2f16;
311 defvar vfloat16m1_t = nxv4f16;
312 defvar vfloat16m2_t = nxv8f16;
313 defvar vfloat16m4_t = nxv16f16;
314 defvar vfloat16m8_t = nxv32f16;
316 defvar vbfloat16mf4_t = nxv1bf16;
317 defvar vbfloat16mf2_t = nxv2bf16;
318 defvar vbfloat16m1_t = nxv4bf16;
319 defvar vbfloat16m2_t = nxv8bf16;
320 defvar vbfloat16m4_t = nxv16bf16;
321 defvar vbfloat16m8_t = nxv32bf16;
323 defvar vfloat32mf2_t = nxv1f32;
324 defvar vfloat32m1_t = nxv2f32;
325 defvar vfloat32m2_t = nxv4f32;
326 defvar vfloat32m4_t = nxv8f32;
327 defvar vfloat32m8_t = nxv16f32;
329 defvar vfloat64m1_t = nxv1f64;
330 defvar vfloat64m2_t = nxv2f64;
331 defvar vfloat64m4_t = nxv4f64;
332 defvar vfloat64m8_t = nxv8f64;
334 defvar vbool1_t = nxv64i1;
335 defvar vbool2_t = nxv32i1;
336 defvar vbool4_t = nxv16i1;
337 defvar vbool8_t = nxv8i1;
338 defvar vbool16_t = nxv4i1;
339 defvar vbool32_t = nxv2i1;
340 defvar vbool64_t = nxv1i1;
342 // There is no need to define register classes for fractional LMUL.
343 defvar LMULList = [1, 2, 4, 8];
345 //===----------------------------------------------------------------------===//
346 // Utility classes for segment load/store.
347 //===----------------------------------------------------------------------===//
348 // The set of legal NF for LMUL = lmul.
349 // LMUL <= 1, NF = 2, 3, 4, 5, 6, 7, 8
350 // LMUL == 2, NF = 2, 3, 4
352 // LMUL == 8, no legal NF
353 class NFList<int lmul> {
354 list<int> L = !cond(!eq(lmul, 8): [],
356 !eq(lmul, 2): [2, 3, 4],
357 true: [2, 3, 4, 5, 6, 7, 8]);
360 // Generate [start, end) SubRegIndex list.
361 class SubRegSet<int nf, int lmul> {
362 list<SubRegIndex> L = !foldl([]<SubRegIndex>,
367 [!cast<SubRegIndex>("sub_vrm" # lmul # "_" # i)],
371 // Collect the valid indexes into 'R' under NF and LMUL values from TUPLE_INDEX.
372 // When NF = 2, the valid TUPLE_INDEX is 0 and 1.
373 // For example, when LMUL = 4, the potential valid indexes is
374 // [8, 12, 16, 20, 24, 28, 4]. However, not all these indexes are valid under
375 // NF = 2. For example, 28 is not valid under LMUL = 4, NF = 2 and TUPLE_INDEX = 0.
377 // (tuple_index + i) x lmul <= (tuple_index x lmul) + 32 - (nf x lmul)
379 // Use START = 0, LMUL = 4 and NF = 2 as the example,
381 // The class will return [8, 12, 16, 20, 24, 4].
382 // Use START = 1, LMUL = 4 and NF = 2 as the example,
384 // The class will return [12, 16, 20, 24, 28, 8].
386 class IndexSet<int tuple_index, int nf, int lmul, bit isV0 = false> {
391 !eq(lmul, 1): !listconcat(!range(8, 32), !range(1, 8)),
392 !eq(lmul, 2): !listconcat(!range(4, 16), !range(1, 4)),
393 !eq(lmul, 4): !listconcat(!range(2, 8), !range(1, 2)))),
396 !if(!le(!mul(!add(i, tuple_index), lmul),
397 !sub(!add(32, !mul(tuple_index, lmul)), !mul(nf, lmul))),
398 [!mul(!add(i, tuple_index), lmul)], [])));
401 // This class returns a list of vector register collections.
402 // For example, for NF = 2 and LMUL = 4,
404 // ([ V8M4, V12M4, V16M4, V20M4, V24M4, V4M4],
405 // [V12M4, V16M4, V20M4, V24M4, V28M4, V8M4])
407 class VRegList<list<dag> LIn, int start, int nf, int lmul, bit isV0> {
413 !foreach(i, IndexSet<start, nf, lmul, isV0>.R,
414 !cast<Register>("V" # i # !cond(!eq(lmul, 2): "M2",
418 !size(IndexSet<start, nf, lmul, isV0>.R)))],
419 VRegList<LIn, !add(start, 1), nf, lmul, isV0>.L));
423 foreach Index = !range(0, 32, 1) in {
424 def V#Index : RISCVReg<Index, "v"#Index>, DwarfRegNum<[!add(Index, 96)]>;
427 foreach Index = !range(0, 32, 2) in {
428 def V#Index#M2 : RISCVRegWithSubRegs<Index, "v"#Index,
429 [!cast<Register>("V"#Index),
430 !cast<Register>("V"#!add(Index, 1))]>,
431 DwarfRegAlias<!cast<Register>("V"#Index)> {
432 let SubRegIndices = [sub_vrm1_0, sub_vrm1_1];
436 foreach Index = !range(0, 32, 4) in {
437 def V#Index#M4 : RISCVRegWithSubRegs<Index, "v"#Index,
438 [!cast<Register>("V"#Index#"M2"),
439 !cast<Register>("V"#!add(Index, 2)#"M2")]>,
440 DwarfRegAlias<!cast<Register>("V"#Index)> {
441 let SubRegIndices = [sub_vrm2_0, sub_vrm2_1];
445 foreach Index = !range(0, 32, 8) in {
446 def V#Index#M8 : RISCVRegWithSubRegs<Index, "v"#Index,
447 [!cast<Register>("V"#Index#"M4"),
448 !cast<Register>("V"#!add(Index, 4)#"M4")]>,
449 DwarfRegAlias<!cast<Register>("V"#Index)> {
450 let SubRegIndices = [sub_vrm4_0, sub_vrm4_1];
454 def VTYPE : RISCVReg<0, "vtype">;
455 def VL : RISCVReg<0, "vl">;
456 def VXSAT : RISCVReg<0, "vxsat">;
457 def VXRM : RISCVReg<0, "vxrm">;
458 let isConstant = true in
459 def VLENB : RISCVReg<0, "vlenb">,
460 DwarfRegNum<[!add(4096, SysRegVLENB.Encoding)]>;
462 def VCSR : RegisterClass<"RISCV", [XLenVT], 32,
463 (add VTYPE, VL, VLENB)> {
464 let RegInfos = XLenRI;
465 let isAllocatable = 0;
469 foreach m = [1, 2, 4] in {
470 foreach n = NFList<m>.L in {
471 def "VN" # n # "M" # m # "NoV0": RegisterTuples<
473 VRegList<[], 0, n, m, false>.L>;
474 def "VN" # n # "M" # m # "V0" : RegisterTuples<
476 VRegList<[], 0, n, m, true>.L>;
480 class VReg<list<ValueType> regTypes, dag regList, int Vlmul>
481 : RegisterClass<"RISCV",
483 64, // The maximum supported ELEN is 64.
486 int Size = !mul(Vlmul, 64);
489 defvar VMaskVTs = [vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t,
490 vbool32_t, vbool64_t];
492 defvar VM1VTs = [vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t,
493 vbfloat16m1_t, vfloat16m1_t, vfloat32m1_t,
494 vfloat64m1_t, vint8mf2_t, vint8mf4_t, vint8mf8_t,
495 vint16mf2_t, vint16mf4_t, vint32mf2_t,
496 vfloat16mf4_t, vfloat16mf2_t, vbfloat16mf4_t,
497 vbfloat16mf2_t, vfloat32mf2_t];
499 defvar VM2VTs = [vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t,
500 vfloat16m2_t, vbfloat16m2_t,
501 vfloat32m2_t, vfloat64m2_t];
503 defvar VM4VTs = [vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t,
504 vfloat16m4_t, vbfloat16m4_t,
505 vfloat32m4_t, vfloat64m4_t];
507 defvar VM8VTs = [vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t,
508 vfloat16m8_t, vbfloat16m8_t,
509 vfloat32m8_t, vfloat64m8_t];
511 def VR : VReg<!listconcat(VM1VTs, VMaskVTs),
512 (add (sequence "V%u", 8, 31),
513 (sequence "V%u", 0, 7)), 1>;
515 def VRNoV0 : VReg<!listconcat(VM1VTs, VMaskVTs),
516 (add (sequence "V%u", 8, 31),
517 (sequence "V%u", 1, 7)), 1>;
519 def VRM2 : VReg<VM2VTs, (add (sequence "V%uM2", 8, 31, 2),
520 (sequence "V%uM2", 0, 7, 2)), 2>;
522 def VRM2NoV0 : VReg<VM2VTs, (add (sequence "V%uM2", 8, 31, 2),
523 (sequence "V%uM2", 2, 7, 2)), 2>;
525 def VRM4 : VReg<VM4VTs,
526 (add V8M4, V12M4, V16M4, V20M4, V24M4, V28M4, V0M4, V4M4), 4>;
528 def VRM4NoV0 : VReg<VM4VTs,
529 (add V8M4, V12M4, V16M4, V20M4, V24M4, V28M4, V4M4), 4>;
531 def VRM8 : VReg<VM8VTs, (add V8M8, V16M8, V24M8, V0M8), 8>;
533 def VRM8NoV0 : VReg<VM8VTs, (add V8M8, V16M8, V24M8), 8>;
535 def VMV0 : RegisterClass<"RISCV", VMaskVTs, 64, (add V0)> {
539 let RegInfos = XLenRI in {
540 def GPRF16 : RegisterClass<"RISCV", [f16], 16, (add GPR)>;
541 def GPRF32 : RegisterClass<"RISCV", [f32], 32, (add GPR)>;
542 } // RegInfos = XLenRI
544 // Dummy zero register for use in the register pair containing X0 (as X1 is
545 // not read to or written when the X0 register pair is used).
546 def DUMMY_REG_PAIR_WITH_X0 : RISCVReg<0, "0">;
548 // Must add DUMMY_REG_PAIR_WITH_X0 to a separate register class to prevent the
549 // register's existence from changing codegen (due to the regPressureSetLimit
550 // for the GPR register class being altered).
551 def GPRAll : GPRRegisterClass<(add GPR, DUMMY_REG_PAIR_WITH_X0)>;
553 let RegAltNameIndices = [ABIRegAltName] in {
554 def X0_Pair : RISCVRegWithSubRegs<0, X0.AsmName,
555 [X0, DUMMY_REG_PAIR_WITH_X0],
557 let SubRegIndices = [sub_gpr_even, sub_gpr_odd];
558 let CoveredBySubRegs = 1;
560 foreach I = 1-15 in {
561 defvar Index = !shl(I, 1);
562 defvar IndexP1 = !add(Index, 1);
563 defvar Reg = !cast<Register>("X"#Index);
564 defvar RegP1 = !cast<Register>("X"#IndexP1);
565 def "X" # Index #"_X" # IndexP1 : RISCVRegWithSubRegs<Index,
569 let SubRegIndices = [sub_gpr_even, sub_gpr_odd];
570 let CoveredBySubRegs = 1;
575 let RegInfos = RegInfoByHwMode<[RV32, RV64],
576 [RegInfo<64, 64, 64>, RegInfo<128, 128, 128>]>,
577 DecoderMethod = "DecodeGPRPairRegisterClass" in
578 def GPRPair : RegisterClass<"RISCV", [XLenPairFVT], 64, (add
579 X10_X11, X12_X13, X14_X15, X16_X17,
583 X18_X19, X20_X21, X22_X23, X24_X25, X26_X27,
584 X0_Pair, X2_X3, X4_X5
587 // The register class is added for inline assembly for vector mask types.
588 def VM : VReg<VMaskVTs,
589 (add (sequence "V%u", 8, 31),
590 (sequence "V%u", 0, 7)), 1>;
592 foreach m = LMULList in {
593 foreach nf = NFList<m>.L in {
594 def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped],
595 (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")),
597 def "VRN" # nf # "M" # m: VReg<[untyped],
598 (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0"),
599 !cast<RegisterTuples>("VN" # nf # "M" # m # "V0")),
605 def FFLAGS : RISCVReg<0, "fflags">;
606 def FRM : RISCVReg<0, "frm">;
608 // Shadow Stack register
609 def SSP : RISCVReg<0, "ssp">;