[RISCV] Fix mgather -> riscv.masked.strided.load combine not extending indices (...
[llvm-project.git] / polly / test / CodeGen / MemAccess / simple___%for.cond---%for.end.jscop.transformed
blobe6c89ce360ce73d68b1427bb73dc11dffd95033e
2    "context" : "{  :  }",
3    "name" : "for.cond => for.end",
4    "statements" : [
5       {
6          "accesses" : [
7             {
8                "kind" : "write",
9                "relation" : "{ Stmt_for_body[i0] -> MemRef_A[0] }"
10             }
11          ],
12          "domain" : "{ Stmt_for_body[i0] : i0 >= 0 and i0 <= 11 }",
13          "name" : "Stmt_for_body",
14          "schedule" : "{ Stmt_for_body[i0] -> [0, i0, 0] }"
15       }
16    ]