clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c

   1 // REQUIRES: powerpc-registered-target
   2 // RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
   3 // RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
   4 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
   5 // RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
   6 // RUN: %clang_cc1 -triple powerpc-unknown-aix \
   7 // RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
   8 // RUN: %clang_cc1 -triple powerpc64-unknown-aix \
   9 // RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
  10
  11 extern unsigned int ui;
  12 extern unsigned long long ull;
  13
  14 void test_builtin_ppc_rldimi() {
  15   // CHECK-LABEL: test_builtin_ppc_rldimi
  16   // CHECK:       %res = alloca i64, align 8
  17   // CHECK-NEXT:  [[RA:%[0-9]+]] = load i64, ptr @ull, align 8
  18   // CHECK-NEXT:  [[RB:%[0-9]+]] = load i64, ptr @ull, align 8
  19   // CHECK-NEXT:  [[RC:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
  20   // CHECK-NEXT:  [[RD:%[0-9]+]] = and i64 [[RC]], 72057593769492480
  21   // CHECK-NEXT:  [[RE:%[0-9]+]] = and i64 [[RB]], -72057593769492481
  22   // CHECK-NEXT:  [[RF:%[0-9]+]] = or i64 [[RD]], [[RE]]
  23   // CHECK-NEXT:  store i64 [[RF]], ptr %res, align 8
  24   // CHECK-NEXT:  ret void
  25
  26   /*shift = 63, mask = 0x00FFFFFFF0000000 = 72057593769492480, ~mask = 0xFF0000000FFFFFFF = -72057593769492481*/
  27   unsigned long long res = __builtin_ppc_rldimi(ull, ull, 63, 0x00FFFFFFF0000000);
  28 }
  29
  30 void test_builtin_ppc_rlwimi() {
  31   // CHECK-LABEL: test_builtin_ppc_rlwimi
  32   // CHECK:       %res = alloca i32, align 4
  33   // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, ptr @ui, align 4
  34   // CHECK-NEXT:  [[RB:%[0-9]+]] = load i32, ptr @ui, align 4
  35   // CHECK-NEXT:  [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
  36   // CHECK-NEXT:  [[RD:%[0-9]+]] = and i32 [[RC]], 16776960
  37   // CHECK-NEXT:  [[RE:%[0-9]+]] = and i32 [[RB]], -16776961
  38   // CHECK-NEXT:  [[RF:%[0-9]+]] = or i32 [[RD]], [[RE]]
  39   // CHECK-NEXT:  store i32 [[RF]], ptr %res, align 4
  40   // CHECK-NEXT:  ret void
  41
  42   /*shift = 31, mask = 0xFFFF00 = 16776960, ~mask = 0xFFFFFFFFFF0000FF = -16776961*/
  43   unsigned int res = __builtin_ppc_rlwimi(ui, ui, 31, 0xFFFF00);
  44 }
  45
  46 void test_builtin_ppc_rlwnm() {
  47   // CHECK-LABEL: test_builtin_ppc_rlwnm
  48   // CHECK:       %res = alloca i32, align 4
  49   // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, ptr @ui, align 4
  50   // CHECK-NEXT:  [[RB:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
  51   // CHECK-NEXT:  [[RC:%[0-9]+]] = and i32 [[RB]], 511
  52   // CHECK-NEXT:  store i32 [[RC]], ptr %res, align 4
  53   // CHECK-NEXT:  ret void
  54
  55   /*shift = 31, mask = 0x1FF = 511*/
  56   unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF);
  57 }
  58
  59 void test_builtin_ppc_rlwnm2(unsigned int shift) {
  60   // CHECK-LABEL: test_builtin_ppc_rlwnm2
  61   // CHECK:       %shift.addr = alloca i32, align 4
  62   // CHECK-NEXT:  %res = alloca i32, align 4
  63   // CHECK-NEXT:  store i32 %shift, ptr %shift.addr, align 4
  64   // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, ptr @ui, align 4
  65   // CHECK-NEXT:  [[RB:%[0-9]+]] = load i32, ptr %shift.addr, align 4
  66   // CHECK-NEXT:  [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 [[RB]])
  67   // CHECK-NEXT:  [[RD:%[0-9]+]] = and i32 [[RC]], 511
  68   // CHECK-NEXT:  store i32 [[RD]], ptr %res, align 4
  69   // CHECK-NEXT:  ret void
  70
  71   /*mask = 0x1FF = 511*/
  72   unsigned int res = __builtin_ppc_rlwnm(ui, shift, 0x1FF);
  73 }
  74
  75 // CHECK-LABEL: @testrotatel4(
  76 // CHECK:         [[TMP:%.*]] = call i32 @llvm.fshl.i32(i32 {{%.*}}, i32 {{%.*}}, i32 {{%.*}})
  77 // CHECK-NEXT:    ret i32 [[TMP]]
  78 //
  79 unsigned int testrotatel4(unsigned int rs, unsigned int shift) {
  80   return __rotatel4(rs, shift);
  81 }
  82
  83 // CHECK-LABEL: @testrotatel8(
  84 // CHECK:         [[TMP:%.*]] = call i64 @llvm.fshl.i64(i64 {{%.*}}, i64 {{%.*}}, i64 {{%.*}})
  85 // CHECK-NEXT:    ret i64 [[TMP]]
  86 //
  87 unsigned long long testrotatel8(unsigned long long rs, unsigned long long shift) {
  88   return __rotatel8(rs, shift);
  89 }
  90
  91 // CHECK-LABEL: @testrdlam(
  92 // CHECK:         [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 {{%.*}}, i64 {{%.*}}, i64 {{%.*}})
  93 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 7
  94 // CHECK-NEXT:    ret i64 [[TMP1]]
  95 //
  96 unsigned long long testrdlam(unsigned long long rs, unsigned int shift) {
  97   // The third parameter is a mask that must be a constant that represents a
  98   // contiguous bit field.
  99   return __rdlam(rs, shift, 7);
 100 }