clang/test/Headers/amdgcn_openmp_device_math_c.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // RUN: %clang_cc1 -internal-isystem %S/Inputs/include -x c -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa -triple powerpc64le-unknown-unknown -D__OFFLOAD_ARCH_gfx90a__ -emit-llvm-bc %s -o %t-host.bc
   3 // RUN: %clang_cc1 -include __clang_hip_runtime_wrapper.h -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_functions.h -internal-isystem %S/../../lib/Headers/openmp_wrappers -internal-isystem %S/Inputs/include -x c -fopenmp -triple amdgcn-amd-amdhsa -aux-triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-host.bc -o - | FileCheck %s --check-prefixes=CHECK
   4 // REQUIRES: amdgpu-registered-target
   5
   6 #include <stdlib.h>
   7 #pragma omp begin declare target
   8
   9 // CHECK-LABEL: @test_math_int(
  10 // CHECK-NEXT:  entry:
  11 // CHECK-NEXT:    [[RETVAL_I:%.*]] = alloca i32, align 4, addrspace(5)
  12 // CHECK-NEXT:    [[__X_ADDR_I:%.*]] = alloca i32, align 4, addrspace(5)
  13 // CHECK-NEXT:    [[__SGN_I:%.*]] = alloca i32, align 4, addrspace(5)
  14 // CHECK-NEXT:    [[X_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
  15 // CHECK-NEXT:    [[L1:%.*]] = alloca i32, align 4, addrspace(5)
  16 // CHECK-NEXT:    [[X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[X_ADDR]] to ptr
  17 // CHECK-NEXT:    [[L1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[L1]] to ptr
  18 // CHECK-NEXT:    store i32 [[X:%.*]], ptr [[X_ADDR_ASCAST]], align 4
  19 // CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[X_ADDR_ASCAST]], align 4
  20 // CHECK-NEXT:    [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr
  21 // CHECK-NEXT:    [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr
  22 // CHECK-NEXT:    [[__SGN_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__SGN_I]] to ptr
  23 // CHECK-NEXT:    store i32 [[TMP0]], ptr [[__X_ADDR_ASCAST_I]], align 4
  24 // CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr [[__X_ADDR_ASCAST_I]], align 4
  25 // CHECK-NEXT:    [[SHR_I:%.*]] = ashr i32 [[TMP1]], 31
  26 // CHECK-NEXT:    store i32 [[SHR_I]], ptr [[__SGN_ASCAST_I]], align 4
  27 // CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[__X_ADDR_ASCAST_I]], align 4
  28 // CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[__SGN_ASCAST_I]], align 4
  29 // CHECK-NEXT:    [[XOR_I:%.*]] = xor i32 [[TMP2]], [[TMP3]]
  30 // CHECK-NEXT:    [[TMP4:%.*]] = load i32, ptr [[__SGN_ASCAST_I]], align 4
  31 // CHECK-NEXT:    [[SUB_I:%.*]] = sub nsw i32 [[XOR_I]], [[TMP4]]
  32 // CHECK-NEXT:    store i32 [[SUB_I]], ptr [[L1_ASCAST]], align 4
  33 // CHECK-NEXT:    ret void
  34 //
  35 void test_math_int(int x) {
  36   int l1 = abs(x);
  37 }
  38
  39 // CHECK-LABEL: @test_math_long(
  40 // CHECK-NEXT:  entry:
  41 // CHECK-NEXT:    [[RETVAL_I:%.*]] = alloca i64, align 8, addrspace(5)
  42 // CHECK-NEXT:    [[__X_ADDR_I:%.*]] = alloca i64, align 8, addrspace(5)
  43 // CHECK-NEXT:    [[__SGN_I:%.*]] = alloca i64, align 8, addrspace(5)
  44 // CHECK-NEXT:    [[X_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
  45 // CHECK-NEXT:    [[L1:%.*]] = alloca i64, align 8, addrspace(5)
  46 // CHECK-NEXT:    [[X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[X_ADDR]] to ptr
  47 // CHECK-NEXT:    [[L1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[L1]] to ptr
  48 // CHECK-NEXT:    store i64 [[X:%.*]], ptr [[X_ADDR_ASCAST]], align 8
  49 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr [[X_ADDR_ASCAST]], align 8
  50 // CHECK-NEXT:    [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr
  51 // CHECK-NEXT:    [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr
  52 // CHECK-NEXT:    [[__SGN_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__SGN_I]] to ptr
  53 // CHECK-NEXT:    store i64 [[TMP0]], ptr [[__X_ADDR_ASCAST_I]], align 8
  54 // CHECK-NEXT:    [[TMP1:%.*]] = load i64, ptr [[__X_ADDR_ASCAST_I]], align 8
  55 // CHECK-NEXT:    [[SHR_I:%.*]] = ashr i64 [[TMP1]], 63
  56 // CHECK-NEXT:    store i64 [[SHR_I]], ptr [[__SGN_ASCAST_I]], align 8
  57 // CHECK-NEXT:    [[TMP2:%.*]] = load i64, ptr [[__X_ADDR_ASCAST_I]], align 8
  58 // CHECK-NEXT:    [[TMP3:%.*]] = load i64, ptr [[__SGN_ASCAST_I]], align 8
  59 // CHECK-NEXT:    [[XOR_I:%.*]] = xor i64 [[TMP2]], [[TMP3]]
  60 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr [[__SGN_ASCAST_I]], align 8
  61 // CHECK-NEXT:    [[SUB_I:%.*]] = sub nsw i64 [[XOR_I]], [[TMP4]]
  62 // CHECK-NEXT:    store i64 [[SUB_I]], ptr [[L1_ASCAST]], align 8
  63 // CHECK-NEXT:    ret void
  64 //
  65 void test_math_long(long x) {
  66   long l1 = labs(x);
  67 }
  68
  69 // CHECK-LABEL: @test_math_long_long(
  70 // CHECK-NEXT:  entry:
  71 // CHECK-NEXT:    [[RETVAL_I:%.*]] = alloca i64, align 8, addrspace(5)
  72 // CHECK-NEXT:    [[__X_ADDR_I:%.*]] = alloca i64, align 8, addrspace(5)
  73 // CHECK-NEXT:    [[__SGN_I:%.*]] = alloca i64, align 8, addrspace(5)
  74 // CHECK-NEXT:    [[X_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
  75 // CHECK-NEXT:    [[L1:%.*]] = alloca i64, align 8, addrspace(5)
  76 // CHECK-NEXT:    [[X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[X_ADDR]] to ptr
  77 // CHECK-NEXT:    [[L1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[L1]] to ptr
  78 // CHECK-NEXT:    store i64 [[X:%.*]], ptr [[X_ADDR_ASCAST]], align 8
  79 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr [[X_ADDR_ASCAST]], align 8
  80 // CHECK-NEXT:    [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr
  81 // CHECK-NEXT:    [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr
  82 // CHECK-NEXT:    [[__SGN_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__SGN_I]] to ptr
  83 // CHECK-NEXT:    store i64 [[TMP0]], ptr [[__X_ADDR_ASCAST_I]], align 8
  84 // CHECK-NEXT:    [[TMP1:%.*]] = load i64, ptr [[__X_ADDR_ASCAST_I]], align 8
  85 // CHECK-NEXT:    [[SHR_I:%.*]] = ashr i64 [[TMP1]], 63
  86 // CHECK-NEXT:    store i64 [[SHR_I]], ptr [[__SGN_ASCAST_I]], align 8
  87 // CHECK-NEXT:    [[TMP2:%.*]] = load i64, ptr [[__X_ADDR_ASCAST_I]], align 8
  88 // CHECK-NEXT:    [[TMP3:%.*]] = load i64, ptr [[__SGN_ASCAST_I]], align 8
  89 // CHECK-NEXT:    [[XOR_I:%.*]] = xor i64 [[TMP2]], [[TMP3]]
  90 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr [[__SGN_ASCAST_I]], align 8
  91 // CHECK-NEXT:    [[SUB_I:%.*]] = sub nsw i64 [[XOR_I]], [[TMP4]]
  92 // CHECK-NEXT:    store i64 [[SUB_I]], ptr [[L1_ASCAST]], align 8
  93 // CHECK-NEXT:    ret void
  94 //
  95 void test_math_long_long(long long x) {
  96   long long l1 = llabs(x);
  97 }
  98
  99 #pragma omp end declare target