| blob | 809bdceb4aa25e1b24222f3bb4f962950c5875d2 |
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3 #
4 # GPR variants should not use INSERT_SUBREG. FPR variants (DUP<ty>lane) should.
6 ...
7 ---
8 name: DUPv4i32gpr
9 legalized: true
10 regBankSelected: true
11 tracksRegLiveness: true
12 body: |
13 bb.0.entry:
14 liveins: $w0
15 ; CHECK-LABEL: name: DUPv4i32gpr
16 ; CHECK: liveins: $w0
17 ; CHECK-NEXT: {{ $}}
18 ; CHECK-NEXT: %copy:gpr32 = COPY $w0
19 ; CHECK-NEXT: %dup:fpr128 = DUPv4i32gpr %copy
20 ; CHECK-NEXT: $q0 = COPY %dup
21 ; CHECK-NEXT: RET_ReallyLR implicit $q0
22 %copy:gpr(s32) = COPY $w0
23 %dup:fpr(<4 x s32>) = G_DUP %copy(s32)
24 $q0 = COPY %dup(<4 x s32>)
25 RET_ReallyLR implicit $q0
27 ...
28 ---
29 name: DUPv2i64gpr
30 alignment: 4
31 legalized: true
32 regBankSelected: true
33 tracksRegLiveness: true
34 body: |
35 bb.0.entry:
36 liveins: $x0
37 ; CHECK-LABEL: name: DUPv2i64gpr
38 ; CHECK: liveins: $x0
39 ; CHECK-NEXT: {{ $}}
40 ; CHECK-NEXT: %copy:gpr64 = COPY $x0
41 ; CHECK-NEXT: %dup:fpr128 = DUPv2i64gpr %copy
42 ; CHECK-NEXT: $q0 = COPY %dup
43 ; CHECK-NEXT: RET_ReallyLR implicit $q0
44 %copy:gpr(s64) = COPY $x0
45 %dup:fpr(<2 x s64>) = G_DUP %copy(s64)
46 $q0 = COPY %dup(<2 x s64>)
47 RET_ReallyLR implicit $q0
49 ...
50 ---
51 name: DUPv2i32gpr
52 alignment: 4
53 legalized: true
54 regBankSelected: true
55 tracksRegLiveness: true
56 body: |
57 bb.0.entry:
58 liveins: $w0
59 ; CHECK-LABEL: name: DUPv2i32gpr
60 ; CHECK: liveins: $w0
61 ; CHECK-NEXT: {{ $}}
62 ; CHECK-NEXT: %copy:gpr32 = COPY $w0
63 ; CHECK-NEXT: %dup:fpr64 = DUPv2i32gpr %copy
64 ; CHECK-NEXT: $d0 = COPY %dup
65 ; CHECK-NEXT: RET_ReallyLR implicit $d0
66 %copy:gpr(s32) = COPY $w0
67 %dup:fpr(<2 x s32>) = G_DUP %copy(s32)
68 $d0 = COPY %dup(<2 x s32>)
69 RET_ReallyLR implicit $d0
71 ...
72 ---
73 name: DUPv4i32lane
74 alignment: 4
75 legalized: true
76 regBankSelected: true
77 tracksRegLiveness: true
78 body: |
79 bb.0.entry:
80 liveins: $s0
82 ; CHECK-LABEL: name: DUPv4i32lane
83 ; CHECK: liveins: $s0
84 ; CHECK-NEXT: {{ $}}
85 ; CHECK-NEXT: %copy:fpr32 = COPY $s0
86 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
87 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.ssub
88 ; CHECK-NEXT: %dup:fpr128 = DUPv4i32lane [[INSERT_SUBREG]], 0
89 ; CHECK-NEXT: $q0 = COPY %dup
90 ; CHECK-NEXT: RET_ReallyLR implicit $q0
91 %copy:fpr(s32) = COPY $s0
92 %dup:fpr(<4 x s32>) = G_DUP %copy(s32)
93 $q0 = COPY %dup(<4 x s32>)
94 RET_ReallyLR implicit $q0
96 ...
97 ---
98 name: DUPv2i64lane
99 alignment: 4
100 legalized: true
101 regBankSelected: true
102 tracksRegLiveness: true
103 body: |
104 bb.0.entry:
105 liveins: $d0
106 ; CHECK-LABEL: name: DUPv2i64lane
107 ; CHECK: liveins: $d0
108 ; CHECK-NEXT: {{ $}}
109 ; CHECK-NEXT: %copy:fpr64 = COPY $d0
110 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
111 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.dsub
112 ; CHECK-NEXT: %dup:fpr128 = DUPv2i64lane [[INSERT_SUBREG]], 0
113 ; CHECK-NEXT: $q0 = COPY %dup
114 ; CHECK-NEXT: RET_ReallyLR implicit $q0
115 %copy:fpr(s64) = COPY $d0
116 %dup:fpr(<2 x s64>) = G_DUP %copy(s64)
117 $q0 = COPY %dup(<2 x s64>)
118 RET_ReallyLR implicit $q0
120 ...
121 ---
122 name: DUPv2i32lane
123 alignment: 4
124 legalized: true
125 regBankSelected: true
126 tracksRegLiveness: true
127 body: |
128 bb.0.entry:
129 liveins: $s0
130 ; CHECK-LABEL: name: DUPv2i32lane
131 ; CHECK: liveins: $s0
132 ; CHECK-NEXT: {{ $}}
133 ; CHECK-NEXT: %copy:fpr32 = COPY $s0
134 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
135 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.ssub
136 ; CHECK-NEXT: %dup:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
137 ; CHECK-NEXT: $d0 = COPY %dup
138 ; CHECK-NEXT: RET_ReallyLR implicit $d0
139 %copy:fpr(s32) = COPY $s0
140 %dup:fpr(<2 x s32>) = G_DUP %copy(s32)
141 $d0 = COPY %dup(<2 x s32>)
142 RET_ReallyLR implicit $d0
145 ...
146 ---
147 name: DUPv4i16lane
148 alignment: 4
149 legalized: true
150 regBankSelected: true
151 tracksRegLiveness: true
152 body: |
153 bb.0.entry:
154 liveins: $h0
155 ; CHECK-LABEL: name: DUPv4i16lane
156 ; CHECK: liveins: $h0
157 ; CHECK-NEXT: {{ $}}
158 ; CHECK-NEXT: %copy:fpr16 = COPY $h0
159 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
160 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.hsub
161 ; CHECK-NEXT: %dup:fpr64 = DUPv4i16lane [[INSERT_SUBREG]], 0
162 ; CHECK-NEXT: $d0 = COPY %dup
163 ; CHECK-NEXT: RET_ReallyLR implicit $d0
164 %copy:fpr(s16) = COPY $h0
165 %dup:fpr(<4 x s16>) = G_DUP %copy(s16)
166 $d0 = COPY %dup(<4 x s16>)
167 RET_ReallyLR implicit $d0
168 ...
169 ---
170 name: DUPv4i16gpr
171 alignment: 4
172 legalized: true
173 regBankSelected: true
174 tracksRegLiveness: true
175 body: |
176 bb.0.entry:
177 liveins: $w0
178 ; CHECK-LABEL: name: DUPv4i16gpr
179 ; CHECK: liveins: $w0
180 ; CHECK-NEXT: {{ $}}
181 ; CHECK-NEXT: %copy:gpr32 = COPY $w0
182 ; CHECK-NEXT: %dup:fpr64 = DUPv4i16gpr %copy
183 ; CHECK-NEXT: $d0 = COPY %dup
184 ; CHECK-NEXT: RET_ReallyLR implicit $d0
185 %copy:gpr(s32) = COPY $w0
186 %dup:fpr(<4 x s16>) = G_DUP %copy(s32)
187 $d0 = COPY %dup(<4 x s16>)
188 RET_ReallyLR implicit $d0
190 ...
191 ---
192 name: DUPv8i16lane
193 alignment: 4
194 legalized: true
195 regBankSelected: true
196 tracksRegLiveness: true
197 body: |
198 bb.0.entry:
199 liveins: $h0
200 ; CHECK-LABEL: name: DUPv8i16lane
201 ; CHECK: liveins: $h0
202 ; CHECK-NEXT: {{ $}}
203 ; CHECK-NEXT: %copy:fpr16 = COPY $h0
204 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
205 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.hsub
206 ; CHECK-NEXT: %dup:fpr128 = DUPv8i16lane [[INSERT_SUBREG]], 0
207 ; CHECK-NEXT: $q0 = COPY %dup
208 ; CHECK-NEXT: RET_ReallyLR implicit $q0
209 %copy:fpr(s16) = COPY $h0
210 %dup:fpr(<8 x s16>) = G_DUP %copy(s16)
211 $q0 = COPY %dup(<8 x s16>)
212 RET_ReallyLR implicit $q0
214 ...
215 ---
216 name: DUPv8i16gpr
217 alignment: 4
218 legalized: true
219 regBankSelected: true
220 tracksRegLiveness: true
221 body: |
222 bb.0.entry:
223 liveins: $w0
224 ; CHECK-LABEL: name: DUPv8i16gpr
225 ; CHECK: liveins: $w0
226 ; CHECK-NEXT: {{ $}}
227 ; CHECK-NEXT: %copy:gpr32 = COPY $w0
228 ; CHECK-NEXT: %dup:fpr128 = DUPv8i16gpr %copy
229 ; CHECK-NEXT: $q0 = COPY %dup
230 ; CHECK-NEXT: RET_ReallyLR implicit $q0
231 %copy:gpr(s32) = COPY $w0
232 %dup:fpr(<8 x s16>) = G_DUP %copy(s32)
233 $q0 = COPY %dup(<8 x s16>)
234 RET_ReallyLR implicit $q0
236 ...
237 ---
238 name: DUPv8i16gpr_s16_src
239 alignment: 4
240 legalized: true
241 regBankSelected: true
242 tracksRegLiveness: true
243 body: |
244 bb.0.entry:
245 liveins: $w0
246 ; CHECK-LABEL: name: DUPv8i16gpr_s16_src
247 ; CHECK: liveins: $w0
248 ; CHECK-NEXT: {{ $}}
249 ; CHECK-NEXT: %copy:gpr32 = COPY $w0
250 ; CHECK-NEXT: %dup:fpr128 = DUPv8i16gpr %copy
251 ; CHECK-NEXT: $q0 = COPY %dup
252 ; CHECK-NEXT: RET_ReallyLR implicit $q0
253 %copy:gpr(s32) = COPY $w0
254 %trunc:gpr(s16) = G_TRUNC %copy
255 %dup:fpr(<8 x s16>) = G_DUP %trunc(s16)
256 $q0 = COPY %dup(<8 x s16>)
257 RET_ReallyLR implicit $q0
259 ...
260 ---
261 name: DUPv4s16gpr_s16_src
262 alignment: 4
263 legalized: true
264 regBankSelected: true
265 tracksRegLiveness: true
266 body: |
267 bb.0.entry:
268 liveins: $w0
269 ; CHECK-LABEL: name: DUPv4s16gpr_s16_src
270 ; CHECK: liveins: $w0
271 ; CHECK-NEXT: {{ $}}
272 ; CHECK-NEXT: %copy:gpr32 = COPY $w0
273 ; CHECK-NEXT: %dup:fpr64 = DUPv4i16gpr %copy
274 ; CHECK-NEXT: $d0 = COPY %dup
275 ; CHECK-NEXT: RET_ReallyLR implicit $d0
276 %copy:gpr(s32) = COPY $w0
277 %trunc:gpr(s16) = G_TRUNC %copy
278 %dup:fpr(<4 x s16>) = G_DUP %trunc(s16)
279 $d0 = COPY %dup(<4 x s16>)
280 RET_ReallyLR implicit $d0
282 ...
283 ---
284 name: DUPv8i8gpr
285 alignment: 4
286 legalized: true
287 regBankSelected: true
288 tracksRegLiveness: true
289 body: |
290 bb.0.entry:
291 liveins: $w0
292 ; CHECK-LABEL: name: DUPv8i8gpr
293 ; CHECK: liveins: $w0
294 ; CHECK-NEXT: {{ $}}
295 ; CHECK-NEXT: %copy:gpr32 = COPY $w0
296 ; CHECK-NEXT: %dup:fpr64 = DUPv8i8gpr %copy
297 ; CHECK-NEXT: $d0 = COPY %dup
298 ; CHECK-NEXT: RET_ReallyLR implicit $d0
299 %copy:gpr(s32) = COPY $w0
300 %dup:fpr(<8 x s8>) = G_DUP %copy(s32)
301 $d0 = COPY %dup(<8 x s8>)
302 RET_ReallyLR implicit $d0
304 ...
305 ---
306 name: DUPv8i8gpr_s8_src
307 alignment: 4
308 legalized: true
309 regBankSelected: true
310 tracksRegLiveness: true
311 body: |
312 bb.0.entry:
313 liveins: $w0
314 ; CHECK-LABEL: name: DUPv8i8gpr_s8_src
315 ; CHECK: liveins: $w0
316 ; CHECK-NEXT: {{ $}}
317 ; CHECK-NEXT: %copy:gpr32 = COPY $w0
318 ; CHECK-NEXT: %dup:fpr64 = DUPv8i8gpr %copy
319 ; CHECK-NEXT: $d0 = COPY %dup
320 ; CHECK-NEXT: RET_ReallyLR implicit $d0
321 %copy:gpr(s32) = COPY $w0
322 %trunc:gpr(s8) = G_TRUNC %copy(s32)
323 %dup:fpr(<8 x s8>) = G_DUP %trunc(s8)
324 $d0 = COPY %dup(<8 x s8>)
325 RET_ReallyLR implicit $d0
327 ...
328 ---
329 name: DUPv16i8gpr
330 alignment: 4
331 legalized: true
332 regBankSelected: true
333 tracksRegLiveness: true
334 body: |
335 bb.0.entry:
336 liveins: $w0
337 ; CHECK-LABEL: name: DUPv16i8gpr
338 ; CHECK: liveins: $w0
339 ; CHECK-NEXT: {{ $}}
340 ; CHECK-NEXT: %copy:gpr32 = COPY $w0
341 ; CHECK-NEXT: %dup:fpr128 = DUPv16i8gpr %copy
342 ; CHECK-NEXT: $q0 = COPY %dup
343 ; CHECK-NEXT: RET_ReallyLR implicit $q0
344 %copy:gpr(s32) = COPY $w0
345 %dup:fpr(<16 x s8>) = G_DUP %copy(s32)
346 $q0 = COPY %dup(<16 x s8>)
347 RET_ReallyLR implicit $q0
348 ...
349 ---
350 name: DUPv16i8gpr_s8_src
351 alignment: 4
352 legalized: true
353 regBankSelected: true
354 tracksRegLiveness: true
355 body: |
356 bb.0.entry:
357 liveins: $w0
358 ; CHECK-LABEL: name: DUPv16i8gpr_s8_src
359 ; CHECK: liveins: $w0
360 ; CHECK-NEXT: {{ $}}
361 ; CHECK-NEXT: %copy:gpr32 = COPY $w0
362 ; CHECK-NEXT: %dup:fpr128 = DUPv16i8gpr %copy
363 ; CHECK-NEXT: $q0 = COPY %dup
364 ; CHECK-NEXT: RET_ReallyLR implicit $q0
365 %copy:gpr(s32) = COPY $w0
366 %trunc:gpr(s8) = G_TRUNC %copy
367 %dup:fpr(<16 x s8>) = G_DUP %trunc(s8)
368 $q0 = COPY %dup(<16 x s8>)
369 RET_ReallyLR implicit $q0
370 ...
371 ---
372 name: dup_v2p0
373 alignment: 4
374 legalized: true
375 regBankSelected: true
376 tracksRegLiveness: true
377 liveins:
378 - { reg: '$x0' }
379 body: |
380 bb.1:
381 liveins: $x0
383 ; CHECK-LABEL: name: dup_v2p0
384 ; CHECK: liveins: $x0
385 ; CHECK-NEXT: {{ $}}
386 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
387 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
388 ; CHECK-NEXT: [[DUPv2i64gpr:%[0-9]+]]:fpr128 = DUPv2i64gpr [[COPY1]]
389 ; CHECK-NEXT: $q0 = COPY [[DUPv2i64gpr]]
390 ; CHECK-NEXT: RET_ReallyLR implicit $q0
391 %0:gpr(p0) = COPY $x0
392 %4:fpr(<2 x p0>) = G_DUP %0(p0)
393 $q0 = COPY %4(<2 x p0>)
394 RET_ReallyLR implicit $q0
396 ...
397 ---
398 name: cst_v4s32
399 legalized: true
400 regBankSelected: true
401 tracksRegLiveness: true
402 body: |
403 bb.0.entry:
404 liveins: $w0
405 ; CHECK-LABEL: name: cst_v4s32
406 ; CHECK: liveins: $w0
407 ; CHECK-NEXT: {{ $}}
408 ; CHECK-NEXT: %dup:fpr128 = MOVIv4i32 3, 0
409 ; CHECK-NEXT: $q0 = COPY %dup
410 ; CHECK-NEXT: RET_ReallyLR implicit $q0
411 %cst:gpr(s32) = G_CONSTANT i32 3
412 %dup:fpr(<4 x s32>) = G_DUP %cst(s32)
413 $q0 = COPY %dup(<4 x s32>)
414 RET_ReallyLR implicit $q0
416 ...
417 ---
418 name: cst_v8s8
419 legalized: true
420 regBankSelected: true
421 tracksRegLiveness: true
422 body: |
423 bb.0.entry:
424 liveins: $w0
425 ; CHECK-LABEL: name: cst_v8s8
426 ; CHECK: liveins: $w0
427 ; CHECK-NEXT: {{ $}}
428 ; CHECK-NEXT: %dup:fpr64 = MOVIv8b_ns 3
429 ; CHECK-NEXT: $d0 = COPY %dup
430 ; CHECK-NEXT: RET_ReallyLR implicit $d0
431 %cst:gpr(s8) = G_CONSTANT i8 3
432 %dup:fpr(<8 x s8>) = G_DUP %cst(s8)
433 $d0 = COPY %dup(<8 x s8>)
434 RET_ReallyLR implicit $d0
435 ...
436 ---
437 name: cst_v2p0
438 legalized: true
439 regBankSelected: true
440 tracksRegLiveness: true
441 body: |
442 bb.0.entry:
443 liveins: $w0
444 ; CHECK-LABEL: name: cst_v2p0
445 ; CHECK: liveins: $w0
446 ; CHECK-NEXT: {{ $}}
447 ; CHECK-NEXT: %cst:gpr64 = MOVi64imm 3
448 ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
449 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
450 ; CHECK-NEXT: $q0 = COPY [[LDRQui]]
451 ; CHECK-NEXT: RET_ReallyLR implicit $q0
452 %cst:gpr(p0) = G_CONSTANT i64 3
453 %dup:fpr(<2 x p0>) = G_DUP %cst(p0)
454 $q0 = COPY %dup(<2 x p0>)
455 RET_ReallyLR implicit $q0