| blob | 4c0d1efb99498fb391e6cc6d082a985f61495e8d |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple aarch64-unknown-linux-gnu | FileCheck %s --check-prefixes=CHECK-SD
3 ; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK-GI
5 ; Tests for wider-than-legal extensions into mul/mla.
7 define <16 x i16> @mul_i16(<16 x i8> %a, <16 x i8> %b) {
8 ; CHECK-SD-LABEL: mul_i16:
9 ; CHECK-SD: // %bb.0: // %entry
10 ; CHECK-SD-NEXT: umull2 v2.8h, v0.16b, v1.16b
11 ; CHECK-SD-NEXT: umull v0.8h, v0.8b, v1.8b
12 ; CHECK-SD-NEXT: mov v1.16b, v2.16b
13 ; CHECK-SD-NEXT: ret
14 ;
15 ; CHECK-GI-LABEL: mul_i16:
16 ; CHECK-GI: // %bb.0: // %entry
17 ; CHECK-GI-NEXT: umull v2.8h, v0.8b, v1.8b
18 ; CHECK-GI-NEXT: umull2 v1.8h, v0.16b, v1.16b
19 ; CHECK-GI-NEXT: mov v0.16b, v2.16b
20 ; CHECK-GI-NEXT: ret
21 entry:
22 %ea = zext <16 x i8> %a to <16 x i16>
23 %eb = zext <16 x i8> %b to <16 x i16>
24 %m = mul <16 x i16> %ea, %eb
25 ret <16 x i16> %m
26 }
28 define <16 x i32> @mul_i32(<16 x i8> %a, <16 x i8> %b) {
29 ; CHECK-SD-LABEL: mul_i32:
30 ; CHECK-SD: // %bb.0: // %entry
31 ; CHECK-SD-NEXT: ushll v2.8h, v0.8b, #0
32 ; CHECK-SD-NEXT: ushll v4.8h, v1.8b, #0
33 ; CHECK-SD-NEXT: ushll2 v5.8h, v0.16b, #0
34 ; CHECK-SD-NEXT: ushll2 v6.8h, v1.16b, #0
35 ; CHECK-SD-NEXT: umull v0.4s, v2.4h, v4.4h
36 ; CHECK-SD-NEXT: umull2 v1.4s, v2.8h, v4.8h
37 ; CHECK-SD-NEXT: umull2 v3.4s, v5.8h, v6.8h
38 ; CHECK-SD-NEXT: umull v2.4s, v5.4h, v6.4h
39 ; CHECK-SD-NEXT: ret
40 ;
41 ; CHECK-GI-LABEL: mul_i32:
42 ; CHECK-GI: // %bb.0: // %entry
43 ; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0
44 ; CHECK-GI-NEXT: ushll v3.8h, v1.8b, #0
45 ; CHECK-GI-NEXT: ushll2 v4.8h, v0.16b, #0
46 ; CHECK-GI-NEXT: ushll2 v5.8h, v1.16b, #0
47 ; CHECK-GI-NEXT: umull v0.4s, v2.4h, v3.4h
48 ; CHECK-GI-NEXT: umull2 v1.4s, v2.8h, v3.8h
49 ; CHECK-GI-NEXT: umull v2.4s, v4.4h, v5.4h
50 ; CHECK-GI-NEXT: umull2 v3.4s, v4.8h, v5.8h
51 ; CHECK-GI-NEXT: ret
52 entry:
53 %ea = zext <16 x i8> %a to <16 x i32>
54 %eb = zext <16 x i8> %b to <16 x i32>
55 %m = mul <16 x i32> %ea, %eb
56 ret <16 x i32> %m
57 }
59 define <16 x i64> @mul_i64(<16 x i8> %a, <16 x i8> %b) {
60 ; CHECK-SD-LABEL: mul_i64:
61 ; CHECK-SD: // %bb.0: // %entry
62 ; CHECK-SD-NEXT: ushll v2.8h, v0.8b, #0
63 ; CHECK-SD-NEXT: ushll2 v0.8h, v0.16b, #0
64 ; CHECK-SD-NEXT: ushll v3.8h, v1.8b, #0
65 ; CHECK-SD-NEXT: ushll2 v1.8h, v1.16b, #0
66 ; CHECK-SD-NEXT: ushll v4.4s, v2.4h, #0
67 ; CHECK-SD-NEXT: ushll v5.4s, v0.4h, #0
68 ; CHECK-SD-NEXT: ushll v6.4s, v3.4h, #0
69 ; CHECK-SD-NEXT: ushll2 v2.4s, v2.8h, #0
70 ; CHECK-SD-NEXT: ushll v16.4s, v1.4h, #0
71 ; CHECK-SD-NEXT: ushll2 v7.4s, v3.8h, #0
72 ; CHECK-SD-NEXT: ushll2 v17.4s, v0.8h, #0
73 ; CHECK-SD-NEXT: ushll2 v18.4s, v1.8h, #0
74 ; CHECK-SD-NEXT: umull2 v1.2d, v4.4s, v6.4s
75 ; CHECK-SD-NEXT: umull v0.2d, v4.2s, v6.2s
76 ; CHECK-SD-NEXT: umull2 v3.2d, v2.4s, v7.4s
77 ; CHECK-SD-NEXT: umull v2.2d, v2.2s, v7.2s
78 ; CHECK-SD-NEXT: umull v4.2d, v5.2s, v16.2s
79 ; CHECK-SD-NEXT: umull2 v7.2d, v17.4s, v18.4s
80 ; CHECK-SD-NEXT: umull2 v5.2d, v5.4s, v16.4s
81 ; CHECK-SD-NEXT: umull v6.2d, v17.2s, v18.2s
82 ; CHECK-SD-NEXT: ret
83 ;
84 ; CHECK-GI-LABEL: mul_i64:
85 ; CHECK-GI: // %bb.0: // %entry
86 ; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0
87 ; CHECK-GI-NEXT: ushll v3.8h, v1.8b, #0
88 ; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0
89 ; CHECK-GI-NEXT: ushll2 v1.8h, v1.16b, #0
90 ; CHECK-GI-NEXT: ushll v4.4s, v2.4h, #0
91 ; CHECK-GI-NEXT: ushll2 v5.4s, v2.8h, #0
92 ; CHECK-GI-NEXT: ushll v2.4s, v3.4h, #0
93 ; CHECK-GI-NEXT: ushll v6.4s, v0.4h, #0
94 ; CHECK-GI-NEXT: ushll2 v3.4s, v3.8h, #0
95 ; CHECK-GI-NEXT: ushll v7.4s, v1.4h, #0
96 ; CHECK-GI-NEXT: ushll2 v16.4s, v0.8h, #0
97 ; CHECK-GI-NEXT: ushll2 v17.4s, v1.8h, #0
98 ; CHECK-GI-NEXT: umull v0.2d, v4.2s, v2.2s
99 ; CHECK-GI-NEXT: umull2 v1.2d, v4.4s, v2.4s
100 ; CHECK-GI-NEXT: umull v2.2d, v5.2s, v3.2s
101 ; CHECK-GI-NEXT: umull2 v3.2d, v5.4s, v3.4s
102 ; CHECK-GI-NEXT: umull v4.2d, v6.2s, v7.2s
103 ; CHECK-GI-NEXT: umull2 v5.2d, v6.4s, v7.4s
104 ; CHECK-GI-NEXT: umull v6.2d, v16.2s, v17.2s
105 ; CHECK-GI-NEXT: umull2 v7.2d, v16.4s, v17.4s
106 ; CHECK-GI-NEXT: ret
107 entry:
108 %ea = zext <16 x i8> %a to <16 x i64>
109 %eb = zext <16 x i8> %b to <16 x i64>
110 %m = mul <16 x i64> %ea, %eb
111 ret <16 x i64> %m
112 }
115 define <16 x i16> @mla_i16(<16 x i8> %a, <16 x i8> %b, <16 x i16> %c) {
116 ; CHECK-SD-LABEL: mla_i16:
117 ; CHECK-SD: // %bb.0: // %entry
118 ; CHECK-SD-NEXT: umlal2 v3.8h, v0.16b, v1.16b
119 ; CHECK-SD-NEXT: umlal v2.8h, v0.8b, v1.8b
120 ; CHECK-SD-NEXT: mov v0.16b, v2.16b
121 ; CHECK-SD-NEXT: mov v1.16b, v3.16b
122 ; CHECK-SD-NEXT: ret
123 ;
124 ; CHECK-GI-LABEL: mla_i16:
125 ; CHECK-GI: // %bb.0: // %entry
126 ; CHECK-GI-NEXT: umlal v2.8h, v0.8b, v1.8b
127 ; CHECK-GI-NEXT: umlal2 v3.8h, v0.16b, v1.16b
128 ; CHECK-GI-NEXT: mov v0.16b, v2.16b
129 ; CHECK-GI-NEXT: mov v1.16b, v3.16b
130 ; CHECK-GI-NEXT: ret
131 entry:
132 %ea = zext <16 x i8> %a to <16 x i16>
133 %eb = zext <16 x i8> %b to <16 x i16>
134 %m = mul <16 x i16> %ea, %eb
135 %d = add <16 x i16> %m, %c
136 ret <16 x i16> %d
137 }
139 define <16 x i32> @mla_i32(<16 x i8> %a, <16 x i8> %b, <16 x i32> %c) {
140 ; CHECK-SD-LABEL: mla_i32:
141 ; CHECK-SD: // %bb.0: // %entry
142 ; CHECK-SD-NEXT: ushll v6.8h, v0.8b, #0
143 ; CHECK-SD-NEXT: ushll v7.8h, v1.8b, #0
144 ; CHECK-SD-NEXT: ushll2 v0.8h, v0.16b, #0
145 ; CHECK-SD-NEXT: ushll2 v1.8h, v1.16b, #0
146 ; CHECK-SD-NEXT: umlal v2.4s, v6.4h, v7.4h
147 ; CHECK-SD-NEXT: umlal2 v3.4s, v6.8h, v7.8h
148 ; CHECK-SD-NEXT: umlal2 v5.4s, v0.8h, v1.8h
149 ; CHECK-SD-NEXT: umlal v4.4s, v0.4h, v1.4h
150 ; CHECK-SD-NEXT: mov v0.16b, v2.16b
151 ; CHECK-SD-NEXT: mov v1.16b, v3.16b
152 ; CHECK-SD-NEXT: mov v2.16b, v4.16b
153 ; CHECK-SD-NEXT: mov v3.16b, v5.16b
154 ; CHECK-SD-NEXT: ret
155 ;
156 ; CHECK-GI-LABEL: mla_i32:
157 ; CHECK-GI: // %bb.0: // %entry
158 ; CHECK-GI-NEXT: ushll v6.8h, v0.8b, #0
159 ; CHECK-GI-NEXT: ushll v7.8h, v1.8b, #0
160 ; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0
161 ; CHECK-GI-NEXT: ushll2 v1.8h, v1.16b, #0
162 ; CHECK-GI-NEXT: umlal v2.4s, v6.4h, v7.4h
163 ; CHECK-GI-NEXT: umlal2 v3.4s, v6.8h, v7.8h
164 ; CHECK-GI-NEXT: umlal v4.4s, v0.4h, v1.4h
165 ; CHECK-GI-NEXT: umlal2 v5.4s, v0.8h, v1.8h
166 ; CHECK-GI-NEXT: mov v0.16b, v2.16b
167 ; CHECK-GI-NEXT: mov v1.16b, v3.16b
168 ; CHECK-GI-NEXT: mov v2.16b, v4.16b
169 ; CHECK-GI-NEXT: mov v3.16b, v5.16b
170 ; CHECK-GI-NEXT: ret
171 entry:
172 %ea = zext <16 x i8> %a to <16 x i32>
173 %eb = zext <16 x i8> %b to <16 x i32>
174 %m = mul <16 x i32> %ea, %eb
175 %d = add <16 x i32> %m, %c
176 ret <16 x i32> %d
177 }
179 define <16 x i64> @mla_i64(<16 x i8> %a, <16 x i8> %b, <16 x i64> %c) {
180 ; CHECK-SD-LABEL: mla_i64:
181 ; CHECK-SD: // %bb.0: // %entry
182 ; CHECK-SD-NEXT: mov v17.16b, v7.16b
183 ; CHECK-SD-NEXT: mov v16.16b, v6.16b
184 ; CHECK-SD-NEXT: ushll v6.8h, v0.8b, #0
185 ; CHECK-SD-NEXT: ushll2 v0.8h, v0.16b, #0
186 ; CHECK-SD-NEXT: ushll v7.8h, v1.8b, #0
187 ; CHECK-SD-NEXT: ushll2 v1.8h, v1.16b, #0
188 ; CHECK-SD-NEXT: ushll v18.4s, v6.4h, #0
189 ; CHECK-SD-NEXT: ushll2 v21.4s, v6.8h, #0
190 ; CHECK-SD-NEXT: ushll v19.4s, v0.4h, #0
191 ; CHECK-SD-NEXT: ushll v20.4s, v7.4h, #0
192 ; CHECK-SD-NEXT: ushll v22.4s, v1.4h, #0
193 ; CHECK-SD-NEXT: ushll2 v23.4s, v7.8h, #0
194 ; CHECK-SD-NEXT: ldp q6, q7, [sp]
195 ; CHECK-SD-NEXT: ushll2 v0.4s, v0.8h, #0
196 ; CHECK-SD-NEXT: ushll2 v1.4s, v1.8h, #0
197 ; CHECK-SD-NEXT: umlal2 v3.2d, v18.4s, v20.4s
198 ; CHECK-SD-NEXT: umlal v2.2d, v18.2s, v20.2s
199 ; CHECK-SD-NEXT: umlal v16.2d, v19.2s, v22.2s
200 ; CHECK-SD-NEXT: umlal2 v5.2d, v21.4s, v23.4s
201 ; CHECK-SD-NEXT: umlal v4.2d, v21.2s, v23.2s
202 ; CHECK-SD-NEXT: umlal2 v17.2d, v19.4s, v22.4s
203 ; CHECK-SD-NEXT: umlal2 v7.2d, v0.4s, v1.4s
204 ; CHECK-SD-NEXT: umlal v6.2d, v0.2s, v1.2s
205 ; CHECK-SD-NEXT: mov v0.16b, v2.16b
206 ; CHECK-SD-NEXT: mov v1.16b, v3.16b
207 ; CHECK-SD-NEXT: mov v2.16b, v4.16b
208 ; CHECK-SD-NEXT: mov v3.16b, v5.16b
209 ; CHECK-SD-NEXT: mov v4.16b, v16.16b
210 ; CHECK-SD-NEXT: mov v5.16b, v17.16b
211 ; CHECK-SD-NEXT: ret
212 ;
213 ; CHECK-GI-LABEL: mla_i64:
214 ; CHECK-GI: // %bb.0: // %entry
215 ; CHECK-GI-NEXT: mov v16.16b, v2.16b
216 ; CHECK-GI-NEXT: mov v17.16b, v3.16b
217 ; CHECK-GI-NEXT: mov v2.16b, v4.16b
218 ; CHECK-GI-NEXT: mov v3.16b, v5.16b
219 ; CHECK-GI-NEXT: mov v4.16b, v6.16b
220 ; CHECK-GI-NEXT: mov v5.16b, v7.16b
221 ; CHECK-GI-NEXT: ushll v6.8h, v0.8b, #0
222 ; CHECK-GI-NEXT: ushll v7.8h, v1.8b, #0
223 ; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0
224 ; CHECK-GI-NEXT: ushll2 v1.8h, v1.16b, #0
225 ; CHECK-GI-NEXT: ushll v18.4s, v6.4h, #0
226 ; CHECK-GI-NEXT: ushll v20.4s, v7.4h, #0
227 ; CHECK-GI-NEXT: ushll2 v19.4s, v6.8h, #0
228 ; CHECK-GI-NEXT: ushll v21.4s, v0.4h, #0
229 ; CHECK-GI-NEXT: ushll2 v22.4s, v7.8h, #0
230 ; CHECK-GI-NEXT: ushll v23.4s, v1.4h, #0
231 ; CHECK-GI-NEXT: ldp q6, q7, [sp]
232 ; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0
233 ; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0
234 ; CHECK-GI-NEXT: umlal v16.2d, v18.2s, v20.2s
235 ; CHECK-GI-NEXT: umlal2 v17.2d, v18.4s, v20.4s
236 ; CHECK-GI-NEXT: umlal v2.2d, v19.2s, v22.2s
237 ; CHECK-GI-NEXT: umlal2 v3.2d, v19.4s, v22.4s
238 ; CHECK-GI-NEXT: umlal v4.2d, v21.2s, v23.2s
239 ; CHECK-GI-NEXT: umlal2 v5.2d, v21.4s, v23.4s
240 ; CHECK-GI-NEXT: umlal v6.2d, v0.2s, v1.2s
241 ; CHECK-GI-NEXT: umlal2 v7.2d, v0.4s, v1.4s
242 ; CHECK-GI-NEXT: mov v0.16b, v16.16b
243 ; CHECK-GI-NEXT: mov v1.16b, v17.16b
244 ; CHECK-GI-NEXT: ret
245 entry:
246 %ea = zext <16 x i8> %a to <16 x i64>
247 %eb = zext <16 x i8> %b to <16 x i64>
248 %m = mul <16 x i64> %ea, %eb
249 %d = add <16 x i64> %m, %c
250 ret <16 x i64> %d
251 }