llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=SI %s
   3 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=VI %s
   4 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
   5 # RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
   6 # RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
   7
   8 ---
   9 name: fabs_s32_ss
  10 legalized: true
  11 regBankSelected: true
  12 tracksRegLiveness: true
  13
  14 body: |
  15   bb.0:
  16     liveins: $sgpr0
  17     ; SI-LABEL: name: fabs_s32_ss
  18     ; SI: liveins: $sgpr0
  19     ; SI-NEXT: {{  $}}
  20     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  21     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
  22     ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
  23     ; SI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
  24     ;
  25     ; VI-LABEL: name: fabs_s32_ss
  26     ; VI: liveins: $sgpr0
  27     ; VI-NEXT: {{  $}}
  28     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  29     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
  30     ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
  31     ; VI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
  32     ;
  33     ; GFX9-LABEL: name: fabs_s32_ss
  34     ; GFX9: liveins: $sgpr0
  35     ; GFX9-NEXT: {{  $}}
  36     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  37     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
  38     ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
  39     ; GFX9-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
  40     ;
  41     ; GFX10-LABEL: name: fabs_s32_ss
  42     ; GFX10: liveins: $sgpr0
  43     ; GFX10-NEXT: {{  $}}
  44     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  45     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
  46     ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
  47     ; GFX10-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
  48     %0:sgpr(s32) = COPY $sgpr0
  49     %1:sgpr(s32) = G_FABS %0
  50     $sgpr0 = COPY %1
  51 ...
  52
  53 ---
  54 name: fabs_s32_vv
  55 legalized: true
  56 regBankSelected: true
  57 tracksRegLiveness: true
  58
  59 body: |
  60   bb.0:
  61     liveins: $vgpr0
  62     ; SI-LABEL: name: fabs_s32_vv
  63     ; SI: liveins: $vgpr0
  64     ; SI-NEXT: {{  $}}
  65     ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  66     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
  67     ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
  68     ; SI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
  69     ;
  70     ; VI-LABEL: name: fabs_s32_vv
  71     ; VI: liveins: $vgpr0
  72     ; VI-NEXT: {{  $}}
  73     ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  74     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
  75     ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
  76     ; VI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
  77     ;
  78     ; GFX9-LABEL: name: fabs_s32_vv
  79     ; GFX9: liveins: $vgpr0
  80     ; GFX9-NEXT: {{  $}}
  81     ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  82     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
  83     ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
  84     ; GFX9-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
  85     ;
  86     ; GFX10-LABEL: name: fabs_s32_vv
  87     ; GFX10: liveins: $vgpr0
  88     ; GFX10-NEXT: {{  $}}
  89     ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  90     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
  91     ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
  92     ; GFX10-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
  93     %0:vgpr(s32) = COPY $vgpr0
  94     %1:vgpr(s32) = G_FABS %0
  95     $vgpr0 = COPY %1
  96 ...
  97
  98 ---
  99 name: fabs_s32_vs
 100 legalized: true
 101 regBankSelected: true
 102 tracksRegLiveness: true
 103
 104 body: |
 105   bb.0:
 106     liveins: $sgpr0
 107     ; SI-LABEL: name: fabs_s32_vs
 108     ; SI: liveins: $sgpr0
 109     ; SI-NEXT: {{  $}}
 110     ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
 111     ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
 112     ; SI-NEXT: $vgpr0 = COPY [[FABS]](s32)
 113     ;
 114     ; VI-LABEL: name: fabs_s32_vs
 115     ; VI: liveins: $sgpr0
 116     ; VI-NEXT: {{  $}}
 117     ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
 118     ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
 119     ; VI-NEXT: $vgpr0 = COPY [[FABS]](s32)
 120     ;
 121     ; GFX9-LABEL: name: fabs_s32_vs
 122     ; GFX9: liveins: $sgpr0
 123     ; GFX9-NEXT: {{  $}}
 124     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
 125     ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
 126     ; GFX9-NEXT: $vgpr0 = COPY [[FABS]](s32)
 127     ;
 128     ; GFX10-LABEL: name: fabs_s32_vs
 129     ; GFX10: liveins: $sgpr0
 130     ; GFX10-NEXT: {{  $}}
 131     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
 132     ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
 133     ; GFX10-NEXT: $vgpr0 = COPY [[FABS]](s32)
 134     %0:sgpr(s32) = COPY $sgpr0
 135     %1:vgpr(s32) = G_FABS %0
 136     $vgpr0 = COPY %1
 137 ...
 138
 139 ---
 140 name: fabs_v2s16_ss
 141 legalized: true
 142 regBankSelected: true
 143 tracksRegLiveness: true
 144
 145 body: |
 146   bb.0:
 147     liveins: $sgpr0_sgpr1
 148     ; SI-LABEL: name: fabs_v2s16_ss
 149     ; SI: liveins: $sgpr0_sgpr1
 150     ; SI-NEXT: {{  $}}
 151     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 152     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
 153     ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
 154     ; SI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
 155     ;
 156     ; VI-LABEL: name: fabs_v2s16_ss
 157     ; VI: liveins: $sgpr0_sgpr1
 158     ; VI-NEXT: {{  $}}
 159     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 160     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
 161     ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
 162     ; VI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
 163     ;
 164     ; GFX9-LABEL: name: fabs_v2s16_ss
 165     ; GFX9: liveins: $sgpr0_sgpr1
 166     ; GFX9-NEXT: {{  $}}
 167     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 168     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
 169     ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
 170     ; GFX9-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
 171     ;
 172     ; GFX10-LABEL: name: fabs_v2s16_ss
 173     ; GFX10: liveins: $sgpr0_sgpr1
 174     ; GFX10-NEXT: {{  $}}
 175     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 176     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
 177     ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
 178     ; GFX10-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
 179     %0:sgpr(<2 x s16>) = COPY $sgpr0
 180     %1:sgpr(<2 x s16>) = G_FABS %0
 181     $sgpr0 = COPY %1
 182 ...
 183
 184 ---
 185 name: fabs_s16_ss
 186 legalized: true
 187 regBankSelected: true
 188 tracksRegLiveness: true
 189
 190 body: |
 191   bb.0:
 192     liveins: $sgpr0
 193     ; SI-LABEL: name: fabs_s16_ss
 194     ; SI: liveins: $sgpr0
 195     ; SI-NEXT: {{  $}}
 196     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 197     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
 198     ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
 199     ; SI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
 200     ;
 201     ; VI-LABEL: name: fabs_s16_ss
 202     ; VI: liveins: $sgpr0
 203     ; VI-NEXT: {{  $}}
 204     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 205     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
 206     ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
 207     ; VI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
 208     ;
 209     ; GFX9-LABEL: name: fabs_s16_ss
 210     ; GFX9: liveins: $sgpr0
 211     ; GFX9-NEXT: {{  $}}
 212     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 213     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
 214     ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
 215     ; GFX9-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
 216     ;
 217     ; GFX10-LABEL: name: fabs_s16_ss
 218     ; GFX10: liveins: $sgpr0
 219     ; GFX10-NEXT: {{  $}}
 220     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 221     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
 222     ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
 223     ; GFX10-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
 224     %0:sgpr(s32) = COPY $sgpr0
 225     %1:sgpr(s16) = G_TRUNC %0
 226     %2:sgpr(s16) = G_FABS %1
 227     %3:sgpr(s32) = G_ANYEXT %2
 228     $sgpr0 = COPY %3
 229 ...
 230
 231 ---
 232 name: fabs_s16_vv
 233 legalized: true
 234 regBankSelected: true
 235 tracksRegLiveness: true
 236
 237 body: |
 238   bb.0:
 239     liveins: $vgpr0
 240     ; SI-LABEL: name: fabs_s16_vv
 241     ; SI: liveins: $vgpr0
 242     ; SI-NEXT: {{  $}}
 243     ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 244     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
 245     ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 246     ; SI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
 247     ;
 248     ; VI-LABEL: name: fabs_s16_vv
 249     ; VI: liveins: $vgpr0
 250     ; VI-NEXT: {{  $}}
 251     ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 252     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
 253     ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 254     ; VI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
 255     ;
 256     ; GFX9-LABEL: name: fabs_s16_vv
 257     ; GFX9: liveins: $vgpr0
 258     ; GFX9-NEXT: {{  $}}
 259     ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 260     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
 261     ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 262     ; GFX9-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
 263     ;
 264     ; GFX10-LABEL: name: fabs_s16_vv
 265     ; GFX10: liveins: $vgpr0
 266     ; GFX10-NEXT: {{  $}}
 267     ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 268     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
 269     ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 270     ; GFX10-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
 271     %0:vgpr(s32) = COPY $vgpr0
 272     %1:vgpr(s16) = G_TRUNC %0
 273     %2:vgpr(s16) = G_FABS %1
 274     %3:vgpr(s32) = G_ANYEXT %2
 275     $vgpr0 = COPY %3
 276 ...
 277
 278 ---
 279 name: fabs_s16_vs
 280 legalized: true
 281 regBankSelected: true
 282 tracksRegLiveness: true
 283
 284 body: |
 285   bb.0:
 286     liveins: $sgpr0
 287
 288     ; SI-LABEL: name: fabs_s16_vs
 289     ; SI: liveins: $sgpr0
 290     ; SI-NEXT: {{  $}}
 291     ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
 292     ; SI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
 293     ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]]
 294     ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16)
 295     ; SI-NEXT: $vgpr0 = COPY [[COPY1]](s32)
 296     ;
 297     ; VI-LABEL: name: fabs_s16_vs
 298     ; VI: liveins: $sgpr0
 299     ; VI-NEXT: {{  $}}
 300     ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
 301     ; VI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
 302     ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]]
 303     ; VI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16)
 304     ; VI-NEXT: $vgpr0 = COPY [[COPY1]](s32)
 305     ;
 306     ; GFX9-LABEL: name: fabs_s16_vs
 307     ; GFX9: liveins: $sgpr0
 308     ; GFX9-NEXT: {{  $}}
 309     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
 310     ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
 311     ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]]
 312     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16)
 313     ; GFX9-NEXT: $vgpr0 = COPY [[COPY1]](s32)
 314     ;
 315     ; GFX10-LABEL: name: fabs_s16_vs
 316     ; GFX10: liveins: $sgpr0
 317     ; GFX10-NEXT: {{  $}}
 318     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
 319     ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
 320     ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]]
 321     ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16)
 322     ; GFX10-NEXT: $vgpr0 = COPY [[COPY1]](s32)
 323     %0:sgpr(s32) = COPY $sgpr0
 324     %1:sgpr(s16) = G_TRUNC %0
 325     %2:vgpr(s16) = G_FABS %1
 326     %3:vgpr(s32) = G_ANYEXT %2
 327     $vgpr0 = COPY %3
 328 ...
 329
 330 ---
 331 name: fabs_v2s16_vv
 332 legalized: true
 333 regBankSelected: true
 334 tracksRegLiveness: true
 335
 336 body: |
 337   bb.0:
 338     liveins: $vgpr0
 339     ; SI-LABEL: name: fabs_v2s16_vv
 340     ; SI: liveins: $vgpr0
 341     ; SI-NEXT: {{  $}}
 342     ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 343     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
 344     ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 345     ; SI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
 346     ;
 347     ; VI-LABEL: name: fabs_v2s16_vv
 348     ; VI: liveins: $vgpr0
 349     ; VI-NEXT: {{  $}}
 350     ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 351     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
 352     ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 353     ; VI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
 354     ;
 355     ; GFX9-LABEL: name: fabs_v2s16_vv
 356     ; GFX9: liveins: $vgpr0
 357     ; GFX9-NEXT: {{  $}}
 358     ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 359     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
 360     ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 361     ; GFX9-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
 362     ;
 363     ; GFX10-LABEL: name: fabs_v2s16_vv
 364     ; GFX10: liveins: $vgpr0
 365     ; GFX10-NEXT: {{  $}}
 366     ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 367     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
 368     ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 369     ; GFX10-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
 370     %0:vgpr(<2 x s16>) = COPY $vgpr0
 371     %1:vgpr(<2 x s16>) = G_FABS %0
 372     $vgpr0 = COPY %1
 373 ...
 374
 375 ---
 376 name: fabs_v2s16_vs
 377 legalized: true
 378 regBankSelected: true
 379 tracksRegLiveness: true
 380
 381 body: |
 382   bb.0:
 383     liveins: $sgpr0
 384     ; SI-LABEL: name: fabs_v2s16_vs
 385     ; SI: liveins: $sgpr0
 386     ; SI-NEXT: {{  $}}
 387     ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
 388     ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
 389     ; SI-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
 390     ;
 391     ; VI-LABEL: name: fabs_v2s16_vs
 392     ; VI: liveins: $sgpr0
 393     ; VI-NEXT: {{  $}}
 394     ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
 395     ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
 396     ; VI-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
 397     ;
 398     ; GFX9-LABEL: name: fabs_v2s16_vs
 399     ; GFX9: liveins: $sgpr0
 400     ; GFX9-NEXT: {{  $}}
 401     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
 402     ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
 403     ; GFX9-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
 404     ;
 405     ; GFX10-LABEL: name: fabs_v2s16_vs
 406     ; GFX10: liveins: $sgpr0
 407     ; GFX10-NEXT: {{  $}}
 408     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
 409     ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
 410     ; GFX10-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
 411     %0:sgpr(<2 x s16>) = COPY $sgpr0
 412     %1:vgpr(<2 x s16>) = G_FABS %0
 413     $vgpr0 = COPY %1
 414 ...
 415
 416 ---
 417 name: fabs_s64_ss
 418 legalized: true
 419 regBankSelected: true
 420 tracksRegLiveness: true
 421
 422 body: |
 423   bb.0:
 424     liveins: $sgpr0_sgpr1
 425     ; SI-LABEL: name: fabs_s64_ss
 426     ; SI: liveins: $sgpr0_sgpr1
 427     ; SI-NEXT: {{  $}}
 428     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 429     ; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 430     ; SI-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 431     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 432     ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
 433     ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
 434     ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 435     ;
 436     ; VI-LABEL: name: fabs_s64_ss
 437     ; VI: liveins: $sgpr0_sgpr1
 438     ; VI-NEXT: {{  $}}
 439     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 440     ; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 441     ; VI-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 442     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 443     ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
 444     ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
 445     ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 446     ;
 447     ; GFX9-LABEL: name: fabs_s64_ss
 448     ; GFX9: liveins: $sgpr0_sgpr1
 449     ; GFX9-NEXT: {{  $}}
 450     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 451     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 452     ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 453     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 454     ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
 455     ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
 456     ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 457     ;
 458     ; GFX10-LABEL: name: fabs_s64_ss
 459     ; GFX10: liveins: $sgpr0_sgpr1
 460     ; GFX10-NEXT: {{  $}}
 461     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 462     ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 463     ; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 464     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 465     ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
 466     ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
 467     ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 468     %0:sgpr(s64) = COPY $sgpr0_sgpr1
 469     %1:sgpr(s64) = G_FABS %0
 470     S_ENDPGM 0, implicit %1
 471 ...
 472
 473 ---
 474 name: fabs_s64_vv
 475 legalized: true
 476 regBankSelected: true
 477 tracksRegLiveness: true
 478
 479 body: |
 480   bb.0:
 481     liveins: $vgpr0_vgpr1
 482     ; SI-LABEL: name: fabs_s64_vv
 483     ; SI: liveins: $vgpr0_vgpr1
 484     ; SI-NEXT: {{  $}}
 485     ; SI-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 486     ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 487     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 488     ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec
 489     ; SI-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 490     ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
 491     ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 492     ;
 493     ; VI-LABEL: name: fabs_s64_vv
 494     ; VI: liveins: $vgpr0_vgpr1
 495     ; VI-NEXT: {{  $}}
 496     ; VI-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 497     ; VI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 498     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 499     ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec
 500     ; VI-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 501     ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
 502     ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 503     ;
 504     ; GFX9-LABEL: name: fabs_s64_vv
 505     ; GFX9: liveins: $vgpr0_vgpr1
 506     ; GFX9-NEXT: {{  $}}
 507     ; GFX9-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 508     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 509     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 510     ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec
 511     ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 512     ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
 513     ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 514     ;
 515     ; GFX10-LABEL: name: fabs_s64_vv
 516     ; GFX10: liveins: $vgpr0_vgpr1
 517     ; GFX10-NEXT: {{  $}}
 518     ; GFX10-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 519     ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 520     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 521     ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec
 522     ; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 523     ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
 524     ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 525     %0:vgpr(s64) = COPY $vgpr0_vgpr1
 526     %1:vgpr(s64) = G_FABS %0
 527     S_ENDPGM 0, implicit %1
 528 ...
 529
 530 ---
 531 name: fabs_s64_vs
 532 legalized: true
 533 regBankSelected: true
 534 tracksRegLiveness: true
 535
 536 body: |
 537   bb.0:
 538     liveins: $sgpr0_sgpr1
 539     ; SI-LABEL: name: fabs_s64_vs
 540     ; SI: liveins: $sgpr0_sgpr1
 541     ; SI-NEXT: {{  $}}
 542     ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
 543     ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]]
 544     ; SI-NEXT: S_ENDPGM 0, implicit [[FABS]](s64)
 545     ;
 546     ; VI-LABEL: name: fabs_s64_vs
 547     ; VI: liveins: $sgpr0_sgpr1
 548     ; VI-NEXT: {{  $}}
 549     ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
 550     ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]]
 551     ; VI-NEXT: S_ENDPGM 0, implicit [[FABS]](s64)
 552     ;
 553     ; GFX9-LABEL: name: fabs_s64_vs
 554     ; GFX9: liveins: $sgpr0_sgpr1
 555     ; GFX9-NEXT: {{  $}}
 556     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
 557     ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]]
 558     ; GFX9-NEXT: S_ENDPGM 0, implicit [[FABS]](s64)
 559     ;
 560     ; GFX10-LABEL: name: fabs_s64_vs
 561     ; GFX10: liveins: $sgpr0_sgpr1
 562     ; GFX10-NEXT: {{  $}}
 563     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
 564     ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]]
 565     ; GFX10-NEXT: S_ENDPGM 0, implicit [[FABS]](s64)
 566     %0:sgpr(s64) = COPY $sgpr0_sgpr1
 567     %1:vgpr(s64) = G_FABS %0
 568     S_ENDPGM 0, implicit %1
 569 ...
 570
 571 # Make sure the source register is constrained
 572 ---
 573 name: fabs_s64_vv_no_src_constraint
 574 legalized: true
 575 regBankSelected: true
 576 tracksRegLiveness: true
 577
 578 body: |
 579   bb.0:
 580     liveins: $vgpr0_vgpr1
 581     ; SI-LABEL: name: fabs_s64_vv_no_src_constraint
 582     ; SI: liveins: $vgpr0_vgpr1
 583     ; SI-NEXT: {{  $}}
 584     ; SI-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
 585     ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
 586     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 587     ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 588     ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
 589     ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
 590     ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 591     ;
 592     ; VI-LABEL: name: fabs_s64_vv_no_src_constraint
 593     ; VI: liveins: $vgpr0_vgpr1
 594     ; VI-NEXT: {{  $}}
 595     ; VI-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
 596     ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
 597     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 598     ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 599     ; VI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
 600     ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
 601     ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 602     ;
 603     ; GFX9-LABEL: name: fabs_s64_vv_no_src_constraint
 604     ; GFX9: liveins: $vgpr0_vgpr1
 605     ; GFX9-NEXT: {{  $}}
 606     ; GFX9-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
 607     ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
 608     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 609     ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 610     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
 611     ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
 612     ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 613     ;
 614     ; GFX10-LABEL: name: fabs_s64_vv_no_src_constraint
 615     ; GFX10: liveins: $vgpr0_vgpr1
 616     ; GFX10-NEXT: {{  $}}
 617     ; GFX10-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
 618     ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
 619     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 620     ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 621     ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
 622     ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
 623     ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 624     %0:vgpr(s64) = IMPLICIT_DEF
 625     %1:vgpr(s64) = G_FABS %0:vgpr(s64)
 626     S_ENDPGM 0, implicit %1
 627 ...
 628
 629 ---
 630 name: fabs_s64_ss_no_src_constraint
 631 legalized: true
 632 regBankSelected: true
 633 tracksRegLiveness: true
 634
 635 body: |
 636   bb.0:
 637     liveins: $sgpr0_sgpr1
 638     ; SI-LABEL: name: fabs_s64_ss_no_src_constraint
 639     ; SI: liveins: $sgpr0_sgpr1
 640     ; SI-NEXT: {{  $}}
 641     ; SI-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
 642     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
 643     ; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
 644     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 645     ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
 646     ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
 647     ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 648     ;
 649     ; VI-LABEL: name: fabs_s64_ss_no_src_constraint
 650     ; VI: liveins: $sgpr0_sgpr1
 651     ; VI-NEXT: {{  $}}
 652     ; VI-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
 653     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
 654     ; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
 655     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 656     ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
 657     ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
 658     ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 659     ;
 660     ; GFX9-LABEL: name: fabs_s64_ss_no_src_constraint
 661     ; GFX9: liveins: $sgpr0_sgpr1
 662     ; GFX9-NEXT: {{  $}}
 663     ; GFX9-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
 664     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
 665     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
 666     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 667     ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
 668     ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
 669     ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 670     ;
 671     ; GFX10-LABEL: name: fabs_s64_ss_no_src_constraint
 672     ; GFX10: liveins: $sgpr0_sgpr1
 673     ; GFX10-NEXT: {{  $}}
 674     ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
 675     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
 676     ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
 677     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 678     ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
 679     ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
 680     ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 681     %0:sgpr(s64) = IMPLICIT_DEF
 682     %1:sgpr(s64) = G_FABS %0:sgpr(s64)
 683     S_ENDPGM 0, implicit %1
 684 ...