llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=MOVREL %s
   3 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GPRIDX %s
   4 # RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=MOVREL %s
   5 # RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=MOVREL %s
   6
   7 ---
   8 name: insert_vector_elt_s_s32_v2s32
   9 legalized: true
  10 regBankSelected: true
  11
  12 body: |
  13   bb.0:
  14     liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
  15
  16     ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v2s32
  17     ; MOVREL: liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
  18     ; MOVREL-NEXT: {{  $}}
  19     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
  20     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  21     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  22     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
  23     ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V2_:%[0-9]+]]:sreg_64 = S_INDIRECT_REG_WRITE_MOVREL_B32_V2 [[COPY]], [[COPY1]], 3, implicit $m0
  24     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V2_]]
  25     ;
  26     ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v2s32
  27     ; GPRIDX: liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
  28     ; GPRIDX-NEXT: {{  $}}
  29     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
  30     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
  31     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
  32     ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
  33     ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V2_:%[0-9]+]]:sreg_64 = S_INDIRECT_REG_WRITE_MOVREL_B32_V2 [[COPY]], [[COPY1]], 3, implicit $m0
  34     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V2_]]
  35     %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
  36     %1:sgpr(s32) = COPY $sgpr2
  37     %2:sgpr(s32) = COPY $sgpr3
  38     %3:sgpr(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
  39     S_ENDPGM 0, implicit %3
  40 ...
  41
  42 ---
  43 name: insert_vector_elt_s_s32_v3s32
  44 legalized: true
  45 regBankSelected: true
  46
  47 body: |
  48   bb.0:
  49     liveins: $sgpr0_sgpr1_sgpr2, $sgpr3, $sgpr4
  50
  51     ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v3s32
  52     ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2, $sgpr3, $sgpr4
  53     ; MOVREL-NEXT: {{  $}}
  54     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_96 = COPY $sgpr0_sgpr1_sgpr2
  55     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  56     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  57     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
  58     ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V3_:%[0-9]+]]:sgpr_96 = S_INDIRECT_REG_WRITE_MOVREL_B32_V3 [[COPY]], [[COPY1]], 3, implicit $m0
  59     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V3_]]
  60     ;
  61     ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v3s32
  62     ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2, $sgpr3, $sgpr4
  63     ; GPRIDX-NEXT: {{  $}}
  64     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_96 = COPY $sgpr0_sgpr1_sgpr2
  65     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  66     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  67     ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
  68     ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V3_:%[0-9]+]]:sgpr_96 = S_INDIRECT_REG_WRITE_MOVREL_B32_V3 [[COPY]], [[COPY1]], 3, implicit $m0
  69     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V3_]]
  70     %0:sgpr(<3 x s32>) = COPY $sgpr0_sgpr1_sgpr2
  71     %1:sgpr(s32) = COPY $sgpr3
  72     %2:sgpr(s32) = COPY $sgpr4
  73     %3:sgpr(<3 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
  74     S_ENDPGM 0, implicit %3
  75 ...
  76
  77 ---
  78 name: insert_vector_elt_s_s32_v4s32
  79 legalized: true
  80 regBankSelected: true
  81
  82 body: |
  83   bb.0:
  84     liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $sgpr5
  85
  86     ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v4s32
  87     ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $sgpr5
  88     ; MOVREL-NEXT: {{  $}}
  89     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
  90     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
  91     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
  92     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
  93     ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0
  94     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_]]
  95     ;
  96     ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v4s32
  97     ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $sgpr5
  98     ; GPRIDX-NEXT: {{  $}}
  99     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 100     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
 101     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
 102     ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
 103     ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0
 104     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_]]
 105     %0:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 106     %1:sgpr(s32) = COPY $sgpr3
 107     %2:sgpr(s32) = COPY $sgpr4
 108     %3:sgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
 109     S_ENDPGM 0, implicit %3
 110 ...
 111
 112 ---
 113 name: insert_vector_elt_s_s32_v5s32
 114 legalized: true
 115 regBankSelected: true
 116
 117 body: |
 118   bb.0:
 119     liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr5, $sgpr6
 120
 121     ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v5s32
 122     ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr5, $sgpr6
 123     ; MOVREL-NEXT: {{  $}}
 124     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_160 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
 125     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
 126     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
 127     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 128     ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V5_:%[0-9]+]]:sgpr_160 = S_INDIRECT_REG_WRITE_MOVREL_B32_V5 [[COPY]], [[COPY1]], 3, implicit $m0
 129     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V5_]]
 130     ;
 131     ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v5s32
 132     ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr5, $sgpr6
 133     ; GPRIDX-NEXT: {{  $}}
 134     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_160 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
 135     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
 136     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
 137     ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
 138     ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V5_:%[0-9]+]]:sgpr_160 = S_INDIRECT_REG_WRITE_MOVREL_B32_V5 [[COPY]], [[COPY1]], 3, implicit $m0
 139     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V5_]]
 140     %0:sgpr(<5 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
 141     %1:sgpr(s32) = COPY $sgpr5
 142     %2:sgpr(s32) = COPY $sgpr6
 143     %3:sgpr(<5 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
 144     S_ENDPGM 0, implicit %3
 145 ...
 146
 147 ---
 148 name: insert_vector_elt_s_s32_v8s32
 149 legalized: true
 150 regBankSelected: true
 151
 152 body: |
 153   bb.0:
 154     liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9
 155
 156     ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v8s32
 157     ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9
 158     ; MOVREL-NEXT: {{  $}}
 159     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
 160     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
 161     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
 162     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 163     ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0
 164     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
 165     ;
 166     ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32
 167     ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9
 168     ; GPRIDX-NEXT: {{  $}}
 169     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
 170     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
 171     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
 172     ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
 173     ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0
 174     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
 175     %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
 176     %1:sgpr(s32) = COPY $sgpr8
 177     %2:sgpr(s32) = COPY $sgpr9
 178     %3:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
 179     S_ENDPGM 0, implicit %3
 180 ...
 181
 182 ---
 183 name: insert_vector_elt_s_s32_v9s32
 184 legalized: true
 185 regBankSelected: true
 186
 187 body: |
 188   bb.0:
 189     liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8, $sgpr9, $sgpr10
 190
 191     ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v9s32
 192     ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8, $sgpr9, $sgpr10
 193     ; MOVREL-NEXT: {{  $}}
 194     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_288 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8
 195     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr9
 196     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr10
 197     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 198     ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V9_:%[0-9]+]]:sgpr_288 = S_INDIRECT_REG_WRITE_MOVREL_B32_V9 [[COPY]], [[COPY1]], 3, implicit $m0
 199     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V9_]]
 200     ;
 201     ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v9s32
 202     ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8, $sgpr9, $sgpr10
 203     ; GPRIDX-NEXT: {{  $}}
 204     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_288 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8
 205     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr9
 206     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr10
 207     ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
 208     ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V9_:%[0-9]+]]:sgpr_288 = S_INDIRECT_REG_WRITE_MOVREL_B32_V9 [[COPY]], [[COPY1]], 3, implicit $m0
 209     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V9_]]
 210     %0:sgpr(<9 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8
 211     %1:sgpr(s32) = COPY $sgpr9
 212     %2:sgpr(s32) = COPY $sgpr10
 213     %3:sgpr(<9 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
 214     S_ENDPGM 0, implicit %3
 215 ...
 216
 217 ---
 218 name: insert_vector_elt_s_s32_v10s32
 219 legalized: true
 220 regBankSelected: true
 221
 222 body: |
 223   bb.0:
 224     liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9, $sgpr10, $sgpr11
 225
 226     ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v10s32
 227     ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9, $sgpr10, $sgpr11
 228     ; MOVREL-NEXT: {{  $}}
 229     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_320 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
 230     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr10
 231     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr11
 232     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 233     ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V10_:%[0-9]+]]:sgpr_320 = S_INDIRECT_REG_WRITE_MOVREL_B32_V10 [[COPY]], [[COPY1]], 3, implicit $m0
 234     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V10_]]
 235     ;
 236     ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v10s32
 237     ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9, $sgpr10, $sgpr11
 238     ; GPRIDX-NEXT: {{  $}}
 239     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_320 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
 240     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr10
 241     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr11
 242     ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
 243     ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V10_:%[0-9]+]]:sgpr_320 = S_INDIRECT_REG_WRITE_MOVREL_B32_V10 [[COPY]], [[COPY1]], 3, implicit $m0
 244     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V10_]]
 245     %0:sgpr(<10 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
 246     %1:sgpr(s32) = COPY $sgpr10
 247     %2:sgpr(s32) = COPY $sgpr11
 248     %3:sgpr(<10 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
 249     S_ENDPGM 0, implicit %3
 250 ...
 251
 252 ---
 253 name: insert_vector_elt_s_s32_v11s32
 254 legalized: true
 255 regBankSelected: true
 256
 257 body: |
 258   bb.0:
 259     liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10, $sgpr11, $sgpr12
 260
 261     ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v11s32
 262     ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10, $sgpr11, $sgpr12
 263     ; MOVREL-NEXT: {{  $}}
 264     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_352 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
 265     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr11
 266     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr12
 267     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 268     ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V11_:%[0-9]+]]:sgpr_352 = S_INDIRECT_REG_WRITE_MOVREL_B32_V11 [[COPY]], [[COPY1]], 3, implicit $m0
 269     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V11_]]
 270     ;
 271     ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v11s32
 272     ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10, $sgpr11, $sgpr12
 273     ; GPRIDX-NEXT: {{  $}}
 274     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_352 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
 275     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr11
 276     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr12
 277     ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
 278     ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V11_:%[0-9]+]]:sgpr_352 = S_INDIRECT_REG_WRITE_MOVREL_B32_V11 [[COPY]], [[COPY1]], 3, implicit $m0
 279     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V11_]]
 280     %0:sgpr(<11 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
 281     %1:sgpr(s32) = COPY $sgpr11
 282     %2:sgpr(s32) = COPY $sgpr12
 283     %3:sgpr(<11 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
 284     S_ENDPGM 0, implicit %3
 285 ...
 286
 287 ---
 288 name: insert_vector_elt_s_s32_v12s32
 289 legalized: true
 290 regBankSelected: true
 291
 292 body: |
 293   bb.0:
 294     liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11, $sgpr12, $sgpr13
 295
 296     ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v12s32
 297     ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11, $sgpr12, $sgpr13
 298     ; MOVREL-NEXT: {{  $}}
 299     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_384 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
 300     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr12
 301     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr13
 302     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 303     ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V12_:%[0-9]+]]:sgpr_384 = S_INDIRECT_REG_WRITE_MOVREL_B32_V12 [[COPY]], [[COPY1]], 3, implicit $m0
 304     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V12_]]
 305     ;
 306     ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v12s32
 307     ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11, $sgpr12, $sgpr13
 308     ; GPRIDX-NEXT: {{  $}}
 309     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_384 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
 310     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr12
 311     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr13
 312     ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
 313     ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V12_:%[0-9]+]]:sgpr_384 = S_INDIRECT_REG_WRITE_MOVREL_B32_V12 [[COPY]], [[COPY1]], 3, implicit $m0
 314     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V12_]]
 315     %0:sgpr(<12 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
 316     %1:sgpr(s32) = COPY $sgpr12
 317     %2:sgpr(s32) = COPY $sgpr13
 318     %3:sgpr(<12 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
 319     S_ENDPGM 0, implicit %3
 320 ...
 321
 322 ---
 323 name: insert_vector_elt_s_s32_v16s32
 324 legalized: true
 325 regBankSelected: true
 326
 327 body: |
 328   bb.0:
 329     liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16, $sgpr17
 330
 331     ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v16s32
 332     ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16, $sgpr17
 333     ; MOVREL-NEXT: {{  $}}
 334     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
 335     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr16
 336     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr17
 337     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 338     ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V16_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B32_V16 [[COPY]], [[COPY1]], 3, implicit $m0
 339     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V16_]]
 340     ;
 341     ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v16s32
 342     ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16, $sgpr17
 343     ; GPRIDX-NEXT: {{  $}}
 344     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
 345     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr16
 346     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr17
 347     ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
 348     ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V16_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B32_V16 [[COPY]], [[COPY1]], 3, implicit $m0
 349     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V16_]]
 350     %0:sgpr(<16 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
 351     %1:sgpr(s32) = COPY $sgpr16
 352     %2:sgpr(s32) = COPY $sgpr17
 353     %3:sgpr(<16 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
 354     S_ENDPGM 0, implicit %3
 355 ...
 356
 357 ---
 358 name: extract_vector_elt_s_s32_v32s32
 359 legalized: true
 360 regBankSelected: true
 361
 362 body: |
 363   bb.0:
 364     liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, $sgpr40, $sgpr41
 365
 366     ; MOVREL-LABEL: name: extract_vector_elt_s_s32_v32s32
 367     ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, $sgpr40, $sgpr41
 368     ; MOVREL-NEXT: {{  $}}
 369     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
 370     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
 371     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr41
 372     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 373     ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V32_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B32_V32 [[COPY]], [[COPY1]], 3, implicit $m0
 374     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V32_]]
 375     ;
 376     ; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v32s32
 377     ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, $sgpr40, $sgpr41
 378     ; GPRIDX-NEXT: {{  $}}
 379     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
 380     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
 381     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr41
 382     ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
 383     ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V32_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B32_V32 [[COPY]], [[COPY1]], 3, implicit $m0
 384     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V32_]]
 385     %0:sgpr(<32 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
 386     %1:sgpr(s32) = COPY $sgpr40
 387     %2:sgpr(s32) = COPY $sgpr41
 388     %3:sgpr(<32 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
 389     S_ENDPGM 0, implicit %3
 390 ...
 391
 392 ---
 393 name: insert_vector_elt_s_s64_v2s64
 394 legalized: true
 395 regBankSelected: true
 396
 397 body: |
 398   bb.0:
 399     liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6
 400
 401     ; MOVREL-LABEL: name: insert_vector_elt_s_s64_v2s64
 402     ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6
 403     ; MOVREL-NEXT: {{  $}}
 404     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 405     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
 406     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
 407     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 408     ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B64_V2 [[COPY]], [[COPY1]], 4, implicit $m0
 409     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_]]
 410     ;
 411     ; GPRIDX-LABEL: name: insert_vector_elt_s_s64_v2s64
 412     ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6
 413     ; GPRIDX-NEXT: {{  $}}
 414     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 415     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
 416     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
 417     ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
 418     ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B64_V2 [[COPY]], [[COPY1]], 4, implicit $m0
 419     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_]]
 420     %0:sgpr(<2 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 421     %1:sgpr(s64) = COPY $sgpr4_sgpr5
 422     %2:sgpr(s32) = COPY $sgpr6
 423     %3:sgpr(<2 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2
 424     S_ENDPGM 0, implicit %3
 425 ...
 426
 427 ---
 428 name: insert_vector_elt_s_s64_v4s64
 429 legalized: true
 430 regBankSelected: true
 431
 432 body: |
 433   bb.0:
 434     liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10
 435
 436     ; MOVREL-LABEL: name: insert_vector_elt_s_s64_v4s64
 437     ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10
 438     ; MOVREL-NEXT: {{  $}}
 439     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
 440     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9
 441     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr10
 442     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 443     ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B64_V4 [[COPY]], [[COPY1]], 4, implicit $m0
 444     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_]]
 445     ;
 446     ; GPRIDX-LABEL: name: insert_vector_elt_s_s64_v4s64
 447     ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10
 448     ; GPRIDX-NEXT: {{  $}}
 449     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
 450     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9
 451     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr10
 452     ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
 453     ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B64_V4 [[COPY]], [[COPY1]], 4, implicit $m0
 454     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_]]
 455     %0:sgpr(<4 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
 456     %1:sgpr(s64) = COPY $sgpr8_sgpr9
 457     %2:sgpr(s32) = COPY $sgpr10
 458     %3:sgpr(<4 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2
 459     S_ENDPGM 0, implicit %3
 460 ...
 461
 462 ---
 463 name: insert_vector_elt_s_s64_v8s64
 464 legalized: true
 465 regBankSelected: true
 466
 467 body: |
 468   bb.0:
 469     liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18
 470
 471     ; MOVREL-LABEL: name: insert_vector_elt_s_s64_v8s64
 472     ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18
 473     ; MOVREL-NEXT: {{  $}}
 474     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
 475     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr16_sgpr17
 476     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18
 477     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 478     ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B64_V8 [[COPY]], [[COPY1]], 4, implicit $m0
 479     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_]]
 480     ;
 481     ; GPRIDX-LABEL: name: insert_vector_elt_s_s64_v8s64
 482     ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18
 483     ; GPRIDX-NEXT: {{  $}}
 484     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
 485     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr16_sgpr17
 486     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18
 487     ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
 488     ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B64_V8 [[COPY]], [[COPY1]], 4, implicit $m0
 489     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_]]
 490     %0:sgpr(<8 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
 491     %1:sgpr(s64) = COPY $sgpr16_sgpr17
 492     %2:sgpr(s32) = COPY $sgpr18
 493     %3:sgpr(<8 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2
 494     S_ENDPGM 0, implicit %3
 495 ...
 496
 497 ---
 498 name: extract_vector_elt_s_s64_v16s64
 499 legalized: true
 500 regBankSelected: true
 501
 502 body: |
 503   bb.0:
 504     liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, $sgpr40_sgpr41, $sgpr42
 505
 506     ; MOVREL-LABEL: name: extract_vector_elt_s_s64_v16s64
 507     ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, $sgpr40_sgpr41, $sgpr42
 508     ; MOVREL-NEXT: {{  $}}
 509     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
 510     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr40_sgpr41
 511     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr42
 512     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 513     ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B64_V16 [[COPY]], [[COPY1]], 4, implicit $m0
 514     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_]]
 515     ;
 516     ; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v16s64
 517     ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, $sgpr40_sgpr41, $sgpr42
 518     ; GPRIDX-NEXT: {{  $}}
 519     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
 520     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr40_sgpr41
 521     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr42
 522     ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
 523     ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B64_V16 [[COPY]], [[COPY1]], 4, implicit $m0
 524     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_]]
 525     %0:sgpr(<16 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
 526     %1:sgpr(s64) = COPY $sgpr40_sgpr41
 527     %2:sgpr(s32) = COPY $sgpr42
 528     %3:sgpr(<16 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2
 529     S_ENDPGM 0, implicit %3
 530 ...
 531
 532 ---
 533 name: insert_vector_elt_vvs_s32_v2s32
 534 legalized: true
 535 regBankSelected: true
 536
 537 body: |
 538   bb.0:
 539     liveins: $vgpr0_vgpr1, $vgpr2, $sgpr3
 540
 541     ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v2s32
 542     ; MOVREL: liveins: $vgpr0_vgpr1, $vgpr2, $sgpr3
 543     ; MOVREL-NEXT: {{  $}}
 544     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 545     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
 546     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
 547     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 548     ; MOVREL-NEXT: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V2_:%[0-9]+]]:vreg_64 = V_INDIRECT_REG_WRITE_MOVREL_B32_V2 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
 549     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V2_]]
 550     ;
 551     ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v2s32
 552     ; GPRIDX: liveins: $vgpr0_vgpr1, $vgpr2, $sgpr3
 553     ; GPRIDX-NEXT: {{  $}}
 554     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 555     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
 556     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
 557     ; GPRIDX-NEXT: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2_:%[0-9]+]]:vreg_64 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec
 558     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2_]]
 559     %0:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
 560     %1:vgpr(s32) = COPY $vgpr2
 561     %2:sgpr(s32) = COPY $sgpr3
 562     %3:vgpr(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
 563     S_ENDPGM 0, implicit %3
 564 ...
 565
 566 ---
 567 name: insert_vector_elt_vvs_s32_v3s32
 568 legalized: true
 569 regBankSelected: true
 570
 571 body: |
 572   bb.0:
 573     liveins: $vgpr0_vgpr1_vgpr2, $vgpr3, $sgpr4
 574
 575     ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v3s32
 576     ; MOVREL: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3, $sgpr4
 577     ; MOVREL-NEXT: {{  $}}
 578     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
 579     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
 580     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
 581     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 582     ; MOVREL-NEXT: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V3_:%[0-9]+]]:vreg_96 = V_INDIRECT_REG_WRITE_MOVREL_B32_V3 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
 583     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V3_]]
 584     ;
 585     ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v3s32
 586     ; GPRIDX: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3, $sgpr4
 587     ; GPRIDX-NEXT: {{  $}}
 588     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
 589     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
 590     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
 591     ; GPRIDX-NEXT: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3_:%[0-9]+]]:vreg_96 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec
 592     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3_]]
 593     %0:vgpr(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
 594     %1:vgpr(s32) = COPY $vgpr3
 595     %2:sgpr(s32) = COPY $sgpr4
 596     %3:vgpr(<3 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
 597     S_ENDPGM 0, implicit %3
 598 ...
 599
 600 ---
 601 name: insert_vector_elt_vvs_s32_v4s32
 602 legalized: true
 603 regBankSelected: true
 604
 605 body: |
 606   bb.0:
 607     liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4, $vgpr5
 608
 609     ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v4s32
 610     ; MOVREL: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4, $vgpr5
 611     ; MOVREL-NEXT: {{  $}}
 612     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
 613     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
 614     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
 615     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 616     ; MOVREL-NEXT: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
 617     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V4_]]
 618     ;
 619     ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v4s32
 620     ; GPRIDX: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4, $vgpr5
 621     ; GPRIDX-NEXT: {{  $}}
 622     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
 623     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
 624     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
 625     ; GPRIDX-NEXT: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec
 626     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4_]]
 627     %0:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
 628     %1:vgpr(s32) = COPY $vgpr3
 629     %2:sgpr(s32) = COPY $sgpr4
 630     %3:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
 631     S_ENDPGM 0, implicit %3
 632 ...
 633
 634 ---
 635 name: insert_vector_elt_vvs_s32_v5s32
 636 legalized: true
 637 regBankSelected: true
 638
 639 body: |
 640   bb.0:
 641     liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5, $sgpr6
 642
 643     ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v5s32
 644     ; MOVREL: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5, $sgpr6
 645     ; MOVREL-NEXT: {{  $}}
 646     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:vreg_160 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
 647     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr5
 648     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
 649     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 650     ; MOVREL-NEXT: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V5_:%[0-9]+]]:vreg_160 = V_INDIRECT_REG_WRITE_MOVREL_B32_V5 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
 651     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V5_]]
 652     ;
 653     ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v5s32
 654     ; GPRIDX: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5, $sgpr6
 655     ; GPRIDX-NEXT: {{  $}}
 656     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:vreg_160 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
 657     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr5
 658     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
 659     ; GPRIDX-NEXT: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5_:%[0-9]+]]:vreg_160 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec
 660     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5_]]
 661     %0:vgpr(<5 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
 662     %1:vgpr(s32) = COPY $vgpr5
 663     %2:sgpr(s32) = COPY $sgpr6
 664     %3:vgpr(<5 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
 665     S_ENDPGM 0, implicit %3
 666 ...
 667
 668 ---
 669 name: insert_vector_elt_vvs_s32_v8s32
 670 legalized: true
 671 regBankSelected: true
 672
 673 body: |
 674   bb.0:
 675     liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9
 676
 677     ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v8s32
 678     ; MOVREL: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9
 679     ; MOVREL-NEXT: {{  $}}
 680     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 681     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
 682     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
 683     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 684     ; MOVREL-NEXT: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
 685     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
 686     ;
 687     ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32
 688     ; GPRIDX: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9
 689     ; GPRIDX-NEXT: {{  $}}
 690     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 691     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
 692     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
 693     ; GPRIDX-NEXT: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec
 694     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_]]
 695     %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 696     %1:vgpr(s32) = COPY $vgpr8
 697     %2:sgpr(s32) = COPY $sgpr9
 698     %3:vgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
 699     S_ENDPGM 0, implicit %3
 700 ...
 701
 702 ---
 703 name: insert_vector_elt_vvs_s32_v8s32_add_1
 704 legalized: true
 705 regBankSelected: true
 706
 707 body: |
 708   bb.0:
 709     liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9
 710
 711     ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_1
 712     ; MOVREL: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9
 713     ; MOVREL-NEXT: {{  $}}
 714     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 715     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
 716     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
 717     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 718     ; MOVREL-NEXT: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 11, implicit $m0, implicit $exec
 719     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
 720     ;
 721     ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_1
 722     ; GPRIDX: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9
 723     ; GPRIDX-NEXT: {{  $}}
 724     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 725     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
 726     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
 727     ; GPRIDX-NEXT: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8 [[COPY]], [[COPY1]], [[COPY2]], 11, implicit-def $m0, implicit $m0, implicit $exec
 728     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_]]
 729     %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 730     %1:vgpr(s32) = COPY $vgpr8
 731     %2:sgpr(s32) = COPY $sgpr9
 732     %3:sgpr(s32) = G_CONSTANT i32 1
 733     %4:sgpr(s32) = G_ADD %2, %3
 734     %5:vgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
 735     S_ENDPGM 0, implicit %5
 736 ...
 737
 738 ---
 739 name: insert_vector_elt_vvs_s32_v8s32_add_8
 740 legalized: true
 741 regBankSelected: true
 742
 743 body: |
 744   bb.0:
 745     liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9
 746
 747     ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_8
 748     ; MOVREL: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9
 749     ; MOVREL-NEXT: {{  $}}
 750     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 751     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
 752     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
 753     ; MOVREL-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
 754     ; MOVREL-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
 755     ; MOVREL-NEXT: $m0 = COPY [[S_ADD_I32_]]
 756     ; MOVREL-NEXT: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
 757     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
 758     ;
 759     ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_8
 760     ; GPRIDX: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9
 761     ; GPRIDX-NEXT: {{  $}}
 762     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 763     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
 764     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
 765     ; GPRIDX-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
 766     ; GPRIDX-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
 767     ; GPRIDX-NEXT: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8 [[COPY]], [[COPY1]], [[S_ADD_I32_]], 3, implicit-def $m0, implicit $m0, implicit $exec
 768     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_]]
 769     %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
 770     %1:vgpr(s32) = COPY $vgpr8
 771     %2:sgpr(s32) = COPY $sgpr9
 772     %3:sgpr(s32) = G_CONSTANT i32 8
 773     %4:sgpr(s32) = G_ADD %2, %3
 774     %5:vgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
 775     S_ENDPGM 0, implicit %5
 776 ...
 777
 778 ---
 779 name: insert_vector_elt_s_s32_v8s32_add_1
 780 legalized: true
 781 regBankSelected: true
 782
 783 body: |
 784   bb.0:
 785     liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9
 786
 787     ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v8s32_add_1
 788     ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9
 789     ; MOVREL-NEXT: {{  $}}
 790     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
 791     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
 792     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
 793     ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
 794     ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 11, implicit $m0
 795     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
 796     ;
 797     ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32_add_1
 798     ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9
 799     ; GPRIDX-NEXT: {{  $}}
 800     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
 801     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
 802     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
 803     ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
 804     ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 11, implicit $m0
 805     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
 806     %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
 807     %1:sgpr(s32) = COPY $sgpr8
 808     %2:sgpr(s32) = COPY $sgpr9
 809     %3:sgpr(s32) = G_CONSTANT i32 1
 810     %4:sgpr(s32) = G_ADD %2, %3
 811     %5:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
 812     S_ENDPGM 0, implicit %5
 813 ...
 814
 815 ---
 816 name: insert_vector_elt_s_s32_v8s32_add_8
 817 legalized: true
 818 regBankSelected: true
 819
 820 body: |
 821   bb.0:
 822     liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9
 823
 824     ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v8s32_add_8
 825     ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9
 826     ; MOVREL-NEXT: {{  $}}
 827     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
 828     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
 829     ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
 830     ; MOVREL-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
 831     ; MOVREL-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
 832     ; MOVREL-NEXT: $m0 = COPY [[S_ADD_I32_]]
 833     ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0
 834     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
 835     ;
 836     ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32_add_8
 837     ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9
 838     ; GPRIDX-NEXT: {{  $}}
 839     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
 840     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
 841     ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
 842     ; GPRIDX-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
 843     ; GPRIDX-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
 844     ; GPRIDX-NEXT: $m0 = COPY [[S_ADD_I32_]]
 845     ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0
 846     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
 847     %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
 848     %1:sgpr(s32) = COPY $sgpr8
 849     %2:sgpr(s32) = COPY $sgpr9
 850     %3:sgpr(s32) = G_CONSTANT i32 8
 851     %4:sgpr(s32) = G_ADD %2, %3
 852     %5:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
 853     S_ENDPGM 0, implicit %5
 854 ...
 855
 856 # This should have been folded out in the legalizer, but make sure it
 857 # doesn't crash.
 858 ---
 859 name: insert_vector_elt_s_s32_v4s32_const_idx
 860 legalized: true
 861 regBankSelected: true
 862
 863 body: |
 864   bb.0:
 865     liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4
 866
 867     ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v4s32_const_idx
 868     ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4
 869     ; MOVREL-NEXT: {{  $}}
 870     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 871     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
 872     ; MOVREL-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
 873     ; MOVREL-NEXT: $m0 = COPY [[S_MOV_B32_]]
 874     ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0
 875     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_]]
 876     ;
 877     ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v4s32_const_idx
 878     ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4
 879     ; GPRIDX-NEXT: {{  $}}
 880     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 881     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
 882     ; GPRIDX-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
 883     ; GPRIDX-NEXT: $m0 = COPY [[S_MOV_B32_]]
 884     ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0
 885     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_]]
 886     %0:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 887     %1:sgpr(s32) = COPY $sgpr4
 888     %2:sgpr(s32) = G_CONSTANT i32 0
 889     %3:sgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
 890     S_ENDPGM 0, implicit %3
 891 ...
 892
 893 ---
 894 name: insert_vector_elt_v_s32_v4s32_const_idx
 895 legalized: true
 896 regBankSelected: true
 897
 898 body: |
 899   bb.0:
 900     liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4
 901
 902     ; MOVREL-LABEL: name: insert_vector_elt_v_s32_v4s32_const_idx
 903     ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4
 904     ; MOVREL-NEXT: {{  $}}
 905     ; MOVREL-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 906     ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
 907     ; MOVREL-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
 908     ; MOVREL-NEXT: $m0 = COPY [[S_MOV_B32_]]
 909     ; MOVREL-NEXT: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
 910     ; MOVREL-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V4_]]
 911     ;
 912     ; GPRIDX-LABEL: name: insert_vector_elt_v_s32_v4s32_const_idx
 913     ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4
 914     ; GPRIDX-NEXT: {{  $}}
 915     ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 916     ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
 917     ; GPRIDX-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
 918     ; GPRIDX-NEXT: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4 [[COPY]], [[COPY1]], [[S_MOV_B32_]], 3, implicit-def $m0, implicit $m0, implicit $exec
 919     ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4_]]
 920     %0:vgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
 921     %1:sgpr(s32) = COPY $sgpr4
 922     %2:sgpr(s32) = G_CONSTANT i32 0
 923     %3:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
 924     S_ENDPGM 0, implicit %3
 925 ...