llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX8 %s
   3 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
   4 # RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
   5 # RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
   6
   7 ---
   8
   9 name:            and_or_s32_sgpr_sgpr_sgpr
  10 legalized:       true
  11 regBankSelected: true
  12 tracksRegLiveness: true
  13
  14 body: |
  15   bb.0:
  16     liveins: $sgpr0, $sgpr1, $sgpr2
  17     ; GFX8-LABEL: name: and_or_s32_sgpr_sgpr_sgpr
  18     ; GFX8: liveins: $sgpr0, $sgpr1, $sgpr2
  19     ; GFX8-NEXT: {{  $}}
  20     ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  21     ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
  22     ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  23     ; GFX8-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
  24     ; GFX8-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def dead $scc
  25     ; GFX8-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
  26     ;
  27     ; GFX9-LABEL: name: and_or_s32_sgpr_sgpr_sgpr
  28     ; GFX9: liveins: $sgpr0, $sgpr1, $sgpr2
  29     ; GFX9-NEXT: {{  $}}
  30     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  31     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
  32     ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  33     ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
  34     ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def dead $scc
  35     ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
  36     %0:sgpr(s32) = COPY $sgpr0
  37     %1:sgpr(s32) = COPY $sgpr1
  38     %2:sgpr(s32) = COPY $sgpr2
  39     %3:sgpr(s32) = G_AND %0, %1
  40     %4:sgpr(s32) = G_OR %3, %2
  41     S_ENDPGM 0, implicit %4
  42 ...
  43
  44 ---
  45
  46 name:            and_or_s32_vgpr_vgpr_vgpr
  47 legalized:       true
  48 regBankSelected: true
  49 tracksRegLiveness: true
  50
  51 body: |
  52   bb.0:
  53     liveins: $vgpr0, $vgpr1, $vgpr2
  54     ; GFX8-LABEL: name: and_or_s32_vgpr_vgpr_vgpr
  55     ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
  56     ; GFX8-NEXT: {{  $}}
  57     ; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  58     ; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  59     ; GFX8-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  60     ; GFX8-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
  61     ; GFX8-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_AND_B32_e64_]], [[COPY2]], implicit $exec
  62     ; GFX8-NEXT: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
  63     ;
  64     ; GFX9-LABEL: name: and_or_s32_vgpr_vgpr_vgpr
  65     ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
  66     ; GFX9-NEXT: {{  $}}
  67     ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  68     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  69     ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  70     ; GFX9-NEXT: [[V_AND_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_OR_B32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
  71     ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_AND_OR_B32_e64_]]
  72     %0:vgpr(s32) = COPY $vgpr0
  73     %1:vgpr(s32) = COPY $vgpr1
  74     %2:vgpr(s32) = COPY $vgpr2
  75     %3:vgpr(s32) = G_AND %0, %1
  76     %4:vgpr(s32) = G_OR %3, %2
  77     S_ENDPGM 0, implicit %4
  78 ...
  79
  80 ---
  81
  82 name:            and_or_s32_vgpr_vgpr_vgpr_commute
  83 legalized:       true
  84 regBankSelected: true
  85 tracksRegLiveness: true
  86
  87 body: |
  88   bb.0:
  89     liveins: $vgpr0, $vgpr1, $vgpr2
  90     ; GFX8-LABEL: name: and_or_s32_vgpr_vgpr_vgpr_commute
  91     ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
  92     ; GFX8-NEXT: {{  $}}
  93     ; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  94     ; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  95     ; GFX8-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  96     ; GFX8-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
  97     ; GFX8-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY2]], [[V_AND_B32_e64_]], implicit $exec
  98     ; GFX8-NEXT: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
  99     ;
 100     ; GFX9-LABEL: name: and_or_s32_vgpr_vgpr_vgpr_commute
 101     ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
 102     ; GFX9-NEXT: {{  $}}
 103     ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 104     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
 105     ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
 106     ; GFX9-NEXT: [[V_AND_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_OR_B32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
 107     ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_AND_OR_B32_e64_]]
 108     %0:vgpr(s32) = COPY $vgpr0
 109     %1:vgpr(s32) = COPY $vgpr1
 110     %2:vgpr(s32) = COPY $vgpr2
 111     %3:vgpr(s32) = G_AND %0, %1
 112     %4:vgpr(s32) = G_OR %2, %3
 113     S_ENDPGM 0, implicit %4
 114 ...
 115
 116 ---
 117
 118 name:            and_or_s32_sgpr_sgpr_vgpr
 119 legalized:       true
 120 regBankSelected: true
 121 tracksRegLiveness: true
 122
 123 body: |
 124   bb.0:
 125     liveins: $sgpr0, $sgpr1, $vgpr0
 126     ; GFX8-LABEL: name: and_or_s32_sgpr_sgpr_vgpr
 127     ; GFX8: liveins: $sgpr0, $sgpr1, $vgpr0
 128     ; GFX8-NEXT: {{  $}}
 129     ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 130     ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 131     ; GFX8-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 132     ; GFX8-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
 133     ; GFX8-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_AND_B32_]]
 134     ; GFX8-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY3]], [[COPY2]], implicit $exec
 135     ; GFX8-NEXT: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
 136     ;
 137     ; GFX9-LABEL: name: and_or_s32_sgpr_sgpr_vgpr
 138     ; GFX9: liveins: $sgpr0, $sgpr1, $vgpr0
 139     ; GFX9-NEXT: {{  $}}
 140     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 141     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 142     ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 143     ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
 144     ; GFX9-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_AND_B32_]]
 145     ; GFX9-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY3]], [[COPY2]], implicit $exec
 146     ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
 147     %0:sgpr(s32) = COPY $sgpr0
 148     %1:sgpr(s32) = COPY $sgpr1
 149     %2:vgpr(s32) = COPY $vgpr0
 150     %3:sgpr(s32) = G_AND %0, %1
 151     %4:vgpr(s32) = COPY %3
 152     %5:vgpr(s32) = G_OR %4, %2
 153     S_ENDPGM 0, implicit %5
 154 ...