[clang][modules] Don't prevent translation of FW_Private includes when explicitly...
[llvm-project.git] / llvm / test / CodeGen / AMDGPU / GlobalISel / inst-select-zext.mir
blob5fa43b1c420793ee463f72c258324a49302c4b4e
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
4 ---
6 name: zext_sgpr_s1_to_sgpr_s16
7 legalized:       true
8 regBankSelected: true
9 body: |
10   bb.0:
11     liveins: $sgpr0
13     ; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s16
14     ; GCN: liveins: $sgpr0
15     ; GCN-NEXT: {{  $}}
16     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
17     ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def dead $scc
18     ; GCN-NEXT: [[S_SEXT_I32_I16_:%[0-9]+]]:sreg_32 = S_SEXT_I32_I16 [[S_AND_B32_]]
19     ; GCN-NEXT: $sgpr0 = COPY [[S_SEXT_I32_I16_]]
20     %0:sgpr(s32) = COPY $sgpr0
21     %1:sgpr(s1) = G_TRUNC %0
22     %2:sgpr(s16) = G_ZEXT %1
23     %3:sgpr(s32) = G_SEXT %2
24     $sgpr0 = COPY %3
25 ...
27 ---
29 name: zext_sgpr_s1_to_sgpr_s32
30 legalized:       true
31 regBankSelected: true
32 body: |
33   bb.0:
34     liveins: $sgpr0
36     ; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s32
37     ; GCN: liveins: $sgpr0
38     ; GCN-NEXT: {{  $}}
39     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
40     ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def dead $scc
41     ; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
42     %0:sgpr(s32) = COPY $sgpr0
43     %1:sgpr(s1) = G_TRUNC %0
44     %2:sgpr(s32) = G_ZEXT %1
45     $sgpr0 = COPY %2
46 ...
48 ---
50 name: zext_sgpr_s1_to_sgpr_s64
51 legalized:       true
52 regBankSelected: true
53 body: |
54   bb.0:
55     liveins: $sgpr0
57     ; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s64
58     ; GCN: liveins: $sgpr0
59     ; GCN-NEXT: {{  $}}
60     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
61     ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
62     ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
63     ; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 65536, implicit-def $scc
64     ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
65     %0:sgpr(s32) = COPY $sgpr0
66     %1:sgpr(s1) = G_TRUNC %0
67     %2:sgpr(s64) = G_ZEXT %1
68     $sgpr0_sgpr1 = COPY %2
69 ...
71 ---
73 name: zext_sgpr_s16_to_sgpr_s32
74 legalized:       true
75 regBankSelected: true
76 body: |
77   bb.0:
78     liveins: $sgpr0
80     ; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s32
81     ; GCN: liveins: $sgpr0
82     ; GCN-NEXT: {{  $}}
83     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
84     ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
85     ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], [[COPY]], implicit-def dead $scc
86     ; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
87     %0:sgpr(s32) = COPY $sgpr0
88     %1:sgpr(s16) = G_TRUNC %0
89     %2:sgpr(s32) = G_ZEXT %1
90     $sgpr0 = COPY %2
92 ...
94 ---
96 name: zext_sgpr_s16_to_sgpr_s64
97 legalized:       true
98 regBankSelected: true
99 body: |
100   bb.0:
101     liveins: $sgpr0
103     ; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s64
104     ; GCN: liveins: $sgpr0
105     ; GCN-NEXT: {{  $}}
106     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
107     ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
108     ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
109     ; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 1048576, implicit-def $scc
110     ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
111     %0:sgpr(s32) = COPY $sgpr0
112     %1:sgpr(s16) = G_TRUNC %0
113     %2:sgpr(s64) = G_ZEXT %1
114     $sgpr0_sgpr1 = COPY %2
120 name: zext_sgpr_s32_to_sgpr_s64
121 legalized:       true
122 regBankSelected: true
123 body: |
124   bb.0:
125     liveins: $sgpr0
127     ; GCN-LABEL: name: zext_sgpr_s32_to_sgpr_s64
128     ; GCN: liveins: $sgpr0
129     ; GCN-NEXT: {{  $}}
130     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY $sgpr0
131     ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
132     ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1
133     ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[REG_SEQUENCE]]
134     %0:sgpr(s32) = COPY $sgpr0
135     %1:sgpr(s64) = G_ZEXT %0
136     $sgpr0_sgpr1 = COPY %1
140 # ---
142 # name: zext_vcc_s1_to_vgpr_s32
143 # legalized:       true
144 # regBankSelected: true
145 # body: |
146 #   bb.0:
147 #     liveins: $vgpr0
149 #     %0:vgpr(s32) = COPY $vgpr0
150 #     %1:vcc(s1) = G_ICMP intpred(eq), %0, %0
151 #     %2:vgpr(s32) = G_ZEXT %1
152 #     $vgpr0 = COPY %2
153 # ...
157 name: zext_vgpr_s1_to_vgpr_s16
158 legalized:       true
159 regBankSelected: true
160 body: |
161   bb.0:
162     liveins: $vgpr0
164     ; GCN-LABEL: name: zext_vgpr_s1_to_vgpr_s16
165     ; GCN: liveins: $vgpr0
166     ; GCN-NEXT: {{  $}}
167     ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
168     ; GCN-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
169     ; GCN-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[V_AND_B32_e32_]], 0, 16, implicit $exec
170     ; GCN-NEXT: $vgpr0 = COPY [[V_BFE_I32_e64_]]
171     %0:vgpr(s32) = COPY $vgpr0
172     %1:vgpr(s1) = G_TRUNC %0
173     %2:vgpr(s16) = G_ZEXT %1
174     %3:vgpr(s32) = G_SEXT %2
175     $vgpr0 = COPY %3
180 name: zext_vgpr_s1_to_vgpr_s32
181 legalized:       true
182 regBankSelected: true
183 body: |
184   bb.0:
185     liveins: $vgpr0
187     ; GCN-LABEL: name: zext_vgpr_s1_to_vgpr_s32
188     ; GCN: liveins: $vgpr0
189     ; GCN-NEXT: {{  $}}
190     ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
191     ; GCN-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
192     ; GCN-NEXT: $vgpr0 = COPY [[V_AND_B32_e32_]]
193     %0:vgpr(s32) = COPY $vgpr0
194     %1:vgpr(s1) = G_TRUNC %0
195     %2:vgpr(s32) = G_ZEXT %1
196     $vgpr0 = COPY %2
201 name: zext_vgpr_s16_to_vgpr_s32
202 legalized:       true
203 regBankSelected: true
204 body: |
205   bb.0:
206     liveins: $vgpr0
208     ; GCN-LABEL: name: zext_vgpr_s16_to_vgpr_s32
209     ; GCN: liveins: $vgpr0
210     ; GCN-NEXT: {{  $}}
211     ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
212     ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
213     ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
214     ; GCN-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
215     %0:vgpr(s32) = COPY $vgpr0
216     %1:vgpr(s16) = G_TRUNC %0
217     %2:vgpr(s32) = G_ZEXT %1
218     $vgpr0 = COPY %2
224 name: zext_sgpr_reg_class_s1_to_sgpr_s32
225 legalized:       true
226 regBankSelected: true
227 body: |
228   bb.0:
229     liveins: $sgpr0
231     ; GCN-LABEL: name: zext_sgpr_reg_class_s1_to_sgpr_s32
232     ; GCN: liveins: $sgpr0
233     ; GCN-NEXT: {{  $}}
234     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
235     ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def dead $scc
236     ; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
237     %0:sgpr(s32) = COPY $sgpr0
238     %1:sreg_32(s1) = G_TRUNC %0
239     %2:sgpr(s32) = G_ZEXT %1
240     $sgpr0 = COPY %2