1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
4 define amdgpu_kernel void @set_inactive(ptr addrspace(1) %out, i32 %in) {
5 ; GCN-LABEL: set_inactive:
7 ; GCN-NEXT: s_load_dword s3, s[0:1], 0x2c
8 ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
9 ; GCN-NEXT: s_mov_b32 s2, -1
10 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
11 ; GCN-NEXT: v_mov_b32_e32 v0, s3
12 ; GCN-NEXT: s_not_b64 exec, exec
13 ; GCN-NEXT: v_mov_b32_e32 v0, 42
14 ; GCN-NEXT: s_not_b64 exec, exec
15 ; GCN-NEXT: s_mov_b32 s3, 0xf000
16 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
18 %tmp = call i32 @llvm.amdgcn.set.inactive.i32(i32 %in, i32 42) #0
19 store i32 %tmp, ptr addrspace(1) %out
23 define amdgpu_kernel void @set_inactive_64(ptr addrspace(1) %out, i64 %in) {
24 ; GCN-LABEL: set_inactive_64:
26 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
27 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
28 ; GCN-NEXT: v_mov_b32_e32 v0, s2
29 ; GCN-NEXT: v_mov_b32_e32 v1, s3
30 ; GCN-NEXT: s_not_b64 exec, exec
31 ; GCN-NEXT: v_mov_b32_e32 v0, 0
32 ; GCN-NEXT: v_mov_b32_e32 v1, 0
33 ; GCN-NEXT: s_not_b64 exec, exec
34 ; GCN-NEXT: s_mov_b32 s2, -1
35 ; GCN-NEXT: s_mov_b32 s3, 0xf000
36 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
38 %tmp = call i64 @llvm.amdgcn.set.inactive.i64(i64 %in, i64 0) #0
39 store i64 %tmp, ptr addrspace(1) %out
43 define amdgpu_kernel void @set_inactive_scc(ptr addrspace(1) %out, i32 %in, <4 x i32> inreg %desc) {
44 ; GCN-LABEL: set_inactive_scc:
46 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
47 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
48 ; GCN-NEXT: s_buffer_load_dword s2, s[4:7], 0x0
49 ; GCN-NEXT: s_load_dword s3, s[0:1], 0x2c
50 ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
51 ; GCN-NEXT: s_mov_b32 s4, 1
52 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
53 ; GCN-NEXT: s_cmp_lg_u32 s2, 56
54 ; GCN-NEXT: s_cselect_b32 s2, 1, 0
55 ; GCN-NEXT: v_mov_b32_e32 v0, s3
56 ; GCN-NEXT: s_not_b64 exec, exec
57 ; GCN-NEXT: v_mov_b32_e32 v0, 42
58 ; GCN-NEXT: s_not_b64 exec, exec
59 ; GCN-NEXT: s_cmp_lg_u32 s2, 0
60 ; GCN-NEXT: s_cbranch_scc0 .LBB2_2
61 ; GCN-NEXT: ; %bb.1: ; %.one
62 ; GCN-NEXT: v_add_u32_e32 v1, vcc, 1, v0
63 ; GCN-NEXT: s_mov_b32 s2, -1
64 ; GCN-NEXT: s_mov_b32 s3, 0xf000
65 ; GCN-NEXT: s_mov_b32 s4, 0
66 ; GCN-NEXT: buffer_store_dword v1, off, s[0:3], 0
67 ; GCN-NEXT: .LBB2_2: ; %Flow
68 ; GCN-NEXT: s_xor_b32 s2, s4, 1
69 ; GCN-NEXT: s_and_b32 s2, s2, 1
70 ; GCN-NEXT: s_cmp_lg_u32 s2, 0
71 ; GCN-NEXT: s_cbranch_scc1 .LBB2_4
72 ; GCN-NEXT: ; %bb.3: ; %.zero
73 ; GCN-NEXT: s_mov_b32 s2, -1
74 ; GCN-NEXT: s_mov_b32 s3, 0xf000
75 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
76 ; GCN-NEXT: .LBB2_4: ; %.exit
78 %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 0, i32 0)
79 %cmp = icmp eq i32 %val, 56
80 %tmp = call i32 @llvm.amdgcn.set.inactive.i32(i32 %in, i32 42) #0
81 br i1 %cmp, label %.zero, label %.one
84 store i32 %tmp, ptr addrspace(1) %out
88 %tmp.1 = add i32 %tmp, 1
89 store i32 %tmp.1, ptr addrspace(1) %out
96 declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) #0
97 declare i64 @llvm.amdgcn.set.inactive.i64(i64, i64) #0
98 declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32)
100 attributes #0 = { convergent readnone }