| blob | 3383b46e7dd8f7d31d5045851b20460eb3345b90 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
4 define float @v_bfi_single_nesting_level(float %x, float %y, float %z) {
5 ; GCN-LABEL: v_bfi_single_nesting_level:
6 ; GCN: ; %bb.0: ; %.entry
7 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8 ; GCN-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2
9 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
10 ; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
11 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
12 ; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
13 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
14 ; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v1
15 ; GCN-NEXT: v_and_b32_e32 v2, 0xc00003ff, v2
16 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v0
17 ; GCN-NEXT: v_or_b32_e32 v1, v1, v2
18 ; GCN-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
19 ; GCN-NEXT: v_or_b32_e32 v0, v1, v0
20 ; GCN-NEXT: s_setpc_b64 s[30:31]
21 .entry:
22 %mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+03
23 %mul.base.i32 = fptoui float %mul.base to i32
24 %y.i32 = fptoui float %y to i32
25 %shl.inner.insert = shl i32 %y.i32, 10
26 %bfi1.and = and i32 %shl.inner.insert, 1047552
27 %bfi1.andnot = and i32 %mul.base.i32, -1073740801
28 %bfi1.or = or i32 %bfi1.and, %bfi1.andnot
29 %mul.outer.insert = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+03
30 %mul.outer.insert.i32 = fptoui float %mul.outer.insert to i32
31 %shl.outer.insert = shl i32 %mul.outer.insert.i32, 20
32 %and.outer = and i32 %shl.outer.insert, 1072693248
33 %or.outer = or i32 %bfi1.or, %and.outer
34 %result = bitcast i32 %or.outer to float
35 ret float %result
36 }
38 define float @v_bfi_single_nesting_level_swapped_operands(float %x, float %y, float %z) {
39 ; GCN-LABEL: v_bfi_single_nesting_level_swapped_operands:
40 ; GCN: ; %bb.0: ; %.entry
41 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
42 ; GCN-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2
43 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
44 ; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
45 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
46 ; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
47 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
48 ; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v1
49 ; GCN-NEXT: v_and_b32_e32 v2, 0xc00003ff, v2
50 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v0
51 ; GCN-NEXT: v_or_b32_e32 v1, v1, v2
52 ; GCN-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
53 ; GCN-NEXT: v_or_b32_e32 v0, v0, v1
54 ; GCN-NEXT: s_setpc_b64 s[30:31]
55 .entry:
56 %mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+03
57 %mul.base.i32 = fptoui float %mul.base to i32
58 %y.i32 = fptoui float %y to i32
59 %shl.inner.insert = shl i32 %y.i32, 10
60 %bfi1.and = and i32 1047552, %shl.inner.insert
61 %bfi1.andnot = and i32 -1073740801, %mul.base.i32
62 %bfi1.or = or i32 %bfi1.and, %bfi1.andnot
63 %mul.outer.insert = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+03
64 %mul.outer.insert.i32 = fptoui float %mul.outer.insert to i32
65 %shl.outer.insert = shl i32 %mul.outer.insert.i32, 20
66 %and.outer = and i32 %shl.outer.insert, 1072693248
67 %or.outer = or i32 %and.outer, %bfi1.or
68 %result = bitcast i32 %or.outer to float
69 ret float %result
70 }
72 define float @v_bfi_single_nesting_level_unbalanced_subtree(float %x, float %y, float %z) {
73 ; GCN-LABEL: v_bfi_single_nesting_level_unbalanced_subtree:
74 ; GCN: ; %bb.0: ; %.entry
75 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
76 ; GCN-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2
77 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
78 ; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
79 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
80 ; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
81 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
82 ; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v1
83 ; GCN-NEXT: v_and_b32_e32 v3, 0x3e0, v2
84 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v0
85 ; GCN-NEXT: v_or_b32_e32 v1, v1, v3
86 ; GCN-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
87 ; GCN-NEXT: v_and_b32_e32 v2, 0xc000001f, v2
88 ; GCN-NEXT: v_or_b32_e32 v1, v2, v1
89 ; GCN-NEXT: v_or_b32_e32 v0, v0, v1
90 ; GCN-NEXT: s_setpc_b64 s[30:31]
91 .entry:
92 %mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+03
93 %mul.base.i32 = fptoui float %mul.base to i32
94 %y.i32 = fptoui float %y to i32
95 %shl.inner.2.insert = shl i32 %y.i32, 10
96 %bfi.inner.2.and.1 = and i32 %shl.inner.2.insert, 1047552
97 %bfi.inner.2.and.2 = and i32 %mul.base.i32, 992
98 %bfi.inner.2 = or i32 %bfi.inner.2.and.1, %bfi.inner.2.and.2
99 %mul.inner.1.insert = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+03
100 %mul.inner.1.insert.1.i32 = fptoui float %mul.inner.1.insert to i32
101 %shl.inner.1.insert.1 = shl i32 %mul.inner.1.insert.1.i32, 20
102 %bfi.inner.1.and.1 = and i32 %shl.inner.1.insert.1, 1072693248
103 %bfi.inner.1.and.2 = and i32 %mul.base.i32, -1073741793
104 %bfi.inner.1 = or i32 %bfi.inner.1.and.2, %bfi.inner.2
105 %bfi.outer = or i32 %bfi.inner.1.and.1, %bfi.inner.1
106 %result = bitcast i32 %bfi.outer to float
107 ret float %result
108 }
110 define float @v_bfi_single_nesting_level_inner_use(float %x, float %y, float %z) {
111 ; GCN-LABEL: v_bfi_single_nesting_level_inner_use:
112 ; GCN: ; %bb.0: ; %.entry
113 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
114 ; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v2
115 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
116 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
117 ; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
118 ; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v1
119 ; GCN-NEXT: v_and_b32_e32 v0, 0x400003ff, v0
120 ; GCN-NEXT: v_or_b32_e32 v0, v1, v0
121 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 1, v0
122 ; GCN-NEXT: s_setpc_b64 s[30:31]
123 .entry:
124 %mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+03
125 %mul.base.i32 = fptoui float %mul.base to i32
126 %y.i32 = fptoui float %y to i32
127 %shl.inner.insert = shl i32 %y.i32, 10
128 %bfi1.and = and i32 %shl.inner.insert, 1047552
129 %bfi1.andnot = and i32 %mul.base.i32, -1073740801
130 %bfi1.or = or i32 %bfi1.and, %bfi1.andnot
131 %mul.outer.insert = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+03
132 %mul.outer.insert.i32 = fptoui float %mul.outer.insert to i32
133 %shl.outer.insert = shl i32 %mul.outer.insert.i32, 20
134 %and.outer = and i32 %shl.outer.insert, 1072693248
135 %or.outer = or i32 %bfi1.or, %and.outer
136 %bfi1.or.seconduse = mul i32 %bfi1.or, 2
137 %result = bitcast i32 %bfi1.or.seconduse to float
138 ret float %result
139 }
141 define float @v_bfi_no_nesting(float %x, float %y, float %z) {
142 ; GCN-LABEL: v_bfi_no_nesting:
143 ; GCN: ; %bb.0: ; %.entry
144 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
145 ; GCN-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2
146 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
147 ; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
148 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
149 ; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
150 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
151 ; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v1
152 ; GCN-NEXT: v_and_b32_e32 v2, 0xc0000400, v2
153 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v0
154 ; GCN-NEXT: v_or_b32_e32 v1, v1, v2
155 ; GCN-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
156 ; GCN-NEXT: v_or_b32_e32 v0, v1, v0
157 ; GCN-NEXT: s_setpc_b64 s[30:31]
158 .entry:
159 %mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+03
160 %mul.base.i32 = fptoui float %mul.base to i32
161 %y.i32 = fptoui float %y to i32
162 %shl.inner.insert = shl i32 %y.i32, 10
163 %inner.and = and i32 %shl.inner.insert, 1047552
164 %inner.and2 = and i32 %mul.base.i32, -1073740800
165 %inner.or = or i32 %inner.and, %inner.and2
166 %mul.outer.insert = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+03
167 %mul.outer.insert.i32 = fptoui float %mul.outer.insert to i32
168 %shl.outer.insert = shl i32 %mul.outer.insert.i32, 20
169 %and.outer = and i32 %shl.outer.insert, 1072693248
170 %or.outer = or i32 %inner.or, %and.outer
171 %result = bitcast i32 %or.outer to float
172 ret float %result
173 }
175 define float @v_bfi_two_levels(float %x, float %y, float %z) {
176 ; GCN-LABEL: v_bfi_two_levels:
177 ; GCN: ; %bb.0: ; %.entry
178 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
179 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
180 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
181 ; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
182 ; GCN-NEXT: v_lshlrev_b32_e32 v3, 5, v1
183 ; GCN-NEXT: v_and_b32_e32 v2, 0xc000001f, v2
184 ; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
185 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
186 ; GCN-NEXT: v_and_b32_e32 v3, 0x3e0, v3
187 ; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v1
188 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v0
189 ; GCN-NEXT: v_or_b32_e32 v2, v3, v2
190 ; GCN-NEXT: v_or_b32_e32 v1, v2, v1
191 ; GCN-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
192 ; GCN-NEXT: v_or_b32_e32 v0, v1, v0
193 ; GCN-NEXT: s_setpc_b64 s[30:31]
194 .entry:
195 %y.i32 = fptoui float %y to i32
196 %shl.insert.inner = shl i32 %y.i32, 5
197 %and.insert.inner = and i32 %shl.insert.inner, 992
198 %z.i32 = fptoui float %z to i32
199 %base.inner = and i32 %z.i32, -1073741793
200 %or.inner = or i32 %and.insert.inner , %base.inner
201 %shl.insert.mid = shl i32 %y.i32, 10
202 %and.insert.mid = and i32 %shl.insert.mid, 1047552
203 %or.mid = or i32 %or.inner, %and.insert.mid
204 %fmul.insert.outer = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+03
205 %cast.insert.outer = fptoui float %fmul.insert.outer to i32
206 %shl.insert.outer = shl i32 %cast.insert.outer, 20
207 %and.insert.outer = and i32 %shl.insert.outer, 1072693248
208 %or.outer = or i32 %or.mid, %and.insert.outer
209 %result = bitcast i32 %or.outer to float
210 ret float %result
211 }
213 define float @v_bfi_two_levels_inner_or_multiple_uses(float %x, float %y, float %z) {
214 ; GCN-LABEL: v_bfi_two_levels_inner_or_multiple_uses:
215 ; GCN: ; %bb.0: ; %.entry
216 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
217 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
218 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
219 ; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
220 ; GCN-NEXT: v_lshlrev_b32_e32 v3, 5, v1
221 ; GCN-NEXT: v_and_b32_e32 v2, 0xc000001f, v2
222 ; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
223 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
224 ; GCN-NEXT: v_and_b32_e32 v3, 0x3e0, v3
225 ; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v1
226 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v0
227 ; GCN-NEXT: v_or_b32_e32 v2, v3, v2
228 ; GCN-NEXT: v_or_b32_e32 v1, v2, v1
229 ; GCN-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
230 ; GCN-NEXT: v_or_b32_e32 v0, v1, v0
231 ; GCN-NEXT: v_mul_f32_e32 v0, v0, v2
232 ; GCN-NEXT: s_setpc_b64 s[30:31]
233 .entry:
234 %y.i32 = fptoui float %y to i32
235 %shl.insert.inner = shl i32 %y.i32, 5
236 %and.insert.inner = and i32 %shl.insert.inner, 992
237 %z.i32 = fptoui float %z to i32
238 %base.inner = and i32 %z.i32, -1073741793
239 %or.inner = or i32 %and.insert.inner , %base.inner
240 %shl.insert.mid = shl i32 %y.i32, 10
241 %and.insert.mid = and i32 %shl.insert.mid, 1047552
242 %or.mid = or i32 %or.inner, %and.insert.mid
243 %fmul.insert.outer = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+03
244 %cast.insert.outer = fptoui float %fmul.insert.outer to i32
245 %shl.insert.outer = shl i32 %cast.insert.outer, 20
246 %and.insert.outer = and i32 %shl.insert.outer, 1072693248
247 %or.outer = or i32 %or.mid, %and.insert.outer
248 %result = bitcast i32 %or.outer to float
249 %or.inner.float = bitcast i32 %or.inner to float
250 %result2 = fmul float %result, %or.inner.float
251 ret float %result2
252 }
254 define float @v_bfi_single_constant_as_partition(float %x, float %y, float %z) {
255 ; GCN-LABEL: v_bfi_single_constant_as_partition:
256 ; GCN: ; %bb.0: ; %.entry
257 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
258 ; GCN-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2
259 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
260 ; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
261 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
262 ; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
263 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
264 ; GCN-NEXT: v_or_b32_e32 v1, v1, v2
265 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v0
266 ; GCN-NEXT: v_or_b32_e32 v0, v1, v0
267 ; GCN-NEXT: s_setpc_b64 s[30:31]
268 .entry:
269 %mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+03
270 %mul.base.i32 = fptoui float %mul.base to i32
271 %y.i32 = fptoui float %y to i32
272 %shl.inner.insert = shl i32 %y.i32, 10
273 %bfi1.or = or i32 %shl.inner.insert, %mul.base.i32
274 %mul.outer.insert = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+03
275 %mul.outer.insert.i32 = fptoui float %mul.outer.insert to i32
276 %shl.outer.insert = shl i32 %mul.outer.insert.i32, 20
277 %and.outer = and i32 %shl.outer.insert, -1
278 %or.outer = or i32 %bfi1.or, %and.outer
279 %result = bitcast i32 %or.outer to float
280 ret float %result
281 }
283 define amdgpu_kernel void @v_bfi_dont_applied_for_scalar_ops(ptr addrspace(1) %out, i16 %a, i32 %b) {
284 ; GCN-LABEL: v_bfi_dont_applied_for_scalar_ops:
285 ; GCN: ; %bb.0:
286 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
287 ; GCN-NEXT: s_mov_b32 s7, 0xf000
288 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
289 ; GCN-NEXT: s_and_b32 s3, s3, 0xffff0000
290 ; GCN-NEXT: s_and_b32 s2, s2, 0xffff
291 ; GCN-NEXT: s_or_b32 s2, s2, s3
292 ; GCN-NEXT: s_mov_b32 s6, -1
293 ; GCN-NEXT: s_mov_b32 s4, s0
294 ; GCN-NEXT: s_mov_b32 s5, s1
295 ; GCN-NEXT: v_mov_b32_e32 v0, s2
296 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
297 ; GCN-NEXT: s_endpgm
298 %shift = lshr i32 %b, 16
299 %tr = trunc i32 %shift to i16
300 %tmp = insertelement <2 x i16> undef, i16 %a, i32 0
301 %vec = insertelement <2 x i16> %tmp, i16 %tr, i32 1
302 %val = bitcast <2 x i16> %vec to i32
303 store i32 %val, ptr addrspace(1) %out, align 4
304 ret void
305 }