| blob | 23e04c517aee656639d52e5f2557df2a23e7fa8a |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SI %s
3 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX8 %s
4 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s
5 ; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
7 define amdgpu_kernel void @v_clamp_add_src_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
8 ; SI-LABEL: v_clamp_add_src_f32:
9 ; SI: ; %bb.0:
10 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
11 ; SI-NEXT: s_mov_b32 s7, 0xf000
12 ; SI-NEXT: s_mov_b32 s6, 0
13 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
14 ; SI-NEXT: v_mov_b32_e32 v1, 0
15 ; SI-NEXT: s_waitcnt lgkmcnt(0)
16 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
17 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
18 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
19 ; SI-NEXT: s_waitcnt vmcnt(0)
20 ; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp
21 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
22 ; SI-NEXT: s_endpgm
23 ;
24 ; GFX8-LABEL: v_clamp_add_src_f32:
25 ; GFX8: ; %bb.0:
26 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
27 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
28 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
29 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
30 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
31 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
32 ; GFX8-NEXT: flat_load_dword v3, v[0:1]
33 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
34 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
35 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
36 ; GFX8-NEXT: s_waitcnt vmcnt(0)
37 ; GFX8-NEXT: v_add_f32_e64 v2, v3, 1.0 clamp
38 ; GFX8-NEXT: flat_store_dword v[0:1], v2
39 ; GFX8-NEXT: s_endpgm
40 ;
41 ; GFX9-LABEL: v_clamp_add_src_f32:
42 ; GFX9: ; %bb.0:
43 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
44 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
45 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
46 ; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
47 ; GFX9-NEXT: s_waitcnt vmcnt(0)
48 ; GFX9-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp
49 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
50 ; GFX9-NEXT: s_endpgm
51 ;
52 ; GFX11-LABEL: v_clamp_add_src_f32:
53 ; GFX11: ; %bb.0:
54 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
55 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
56 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
57 ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
58 ; GFX11-NEXT: s_waitcnt vmcnt(0)
59 ; GFX11-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp
60 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
61 ; GFX11-NEXT: s_nop 0
62 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
63 ; GFX11-NEXT: s_endpgm
64 %tid = call i32 @llvm.amdgcn.workitem.id.x()
65 %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
66 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
67 %a = load float, ptr addrspace(1) %gep0
68 %add = fadd float %a, 1.0
69 %max = call float @llvm.maxnum.f32(float %add, float 0.0)
70 %clamp = call float @llvm.minnum.f32(float %max, float 1.0)
71 store float %clamp, ptr addrspace(1) %out.gep
72 ret void
73 }
75 define amdgpu_kernel void @v_clamp_multi_use_src_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
76 ; SI-LABEL: v_clamp_multi_use_src_f32:
77 ; SI: ; %bb.0:
78 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
79 ; SI-NEXT: s_mov_b32 s6, 0
80 ; SI-NEXT: s_mov_b32 s7, 0xf000
81 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
82 ; SI-NEXT: v_mov_b32_e32 v1, 0
83 ; SI-NEXT: s_waitcnt lgkmcnt(0)
84 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
85 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
86 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
87 ; SI-NEXT: s_mov_b32 s6, -1
88 ; SI-NEXT: s_waitcnt vmcnt(0)
89 ; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
90 ; SI-NEXT: v_max_f32_e64 v3, v2, v2 clamp
91 ; SI-NEXT: buffer_store_dword v3, v[0:1], s[0:3], 0 addr64
92 ; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0
93 ; SI-NEXT: s_waitcnt vmcnt(0)
94 ; SI-NEXT: s_endpgm
95 ;
96 ; GFX8-LABEL: v_clamp_multi_use_src_f32:
97 ; GFX8: ; %bb.0:
98 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
99 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
100 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
101 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
102 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
103 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
104 ; GFX8-NEXT: flat_load_dword v3, v[0:1]
105 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
106 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
107 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
108 ; GFX8-NEXT: s_waitcnt vmcnt(0)
109 ; GFX8-NEXT: v_add_f32_e32 v2, 1.0, v3
110 ; GFX8-NEXT: v_max_f32_e64 v3, v2, v2 clamp
111 ; GFX8-NEXT: flat_store_dword v[0:1], v3
112 ; GFX8-NEXT: flat_store_dword v[0:1], v2
113 ; GFX8-NEXT: s_waitcnt vmcnt(0)
114 ; GFX8-NEXT: s_endpgm
115 ;
116 ; GFX9-LABEL: v_clamp_multi_use_src_f32:
117 ; GFX9: ; %bb.0:
118 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
119 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
120 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
121 ; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
122 ; GFX9-NEXT: s_waitcnt vmcnt(0)
123 ; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
124 ; GFX9-NEXT: v_max_f32_e64 v2, v1, v1 clamp
125 ; GFX9-NEXT: global_store_dword v0, v2, s[0:1]
126 ; GFX9-NEXT: global_store_dword v[0:1], v1, off
127 ; GFX9-NEXT: s_waitcnt vmcnt(0)
128 ; GFX9-NEXT: s_endpgm
129 ;
130 ; GFX11-LABEL: v_clamp_multi_use_src_f32:
131 ; GFX11: ; %bb.0:
132 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
133 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
134 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
135 ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
136 ; GFX11-NEXT: s_waitcnt vmcnt(0)
137 ; GFX11-NEXT: v_add_f32_e32 v1, 1.0, v1
138 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
139 ; GFX11-NEXT: v_max_f32_e64 v2, v1, v1 clamp
140 ; GFX11-NEXT: global_store_b32 v0, v2, s[0:1]
141 ; GFX11-NEXT: global_store_b32 v[0:1], v1, off dlc
142 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
143 ; GFX11-NEXT: s_nop 0
144 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
145 ; GFX11-NEXT: s_endpgm
146 %tid = call i32 @llvm.amdgcn.workitem.id.x()
147 %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
148 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
149 %a = load float, ptr addrspace(1) %gep0
150 %add = fadd float %a, 1.0
151 %max = call float @llvm.maxnum.f32(float %add, float 0.0)
152 %clamp = call float @llvm.minnum.f32(float %max, float 1.0)
153 store float %clamp, ptr addrspace(1) %out.gep
154 store volatile float %add, ptr addrspace(1) undef
155 ret void
156 }
158 define amdgpu_kernel void @v_clamp_dbg_use_src_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
159 ; SI-LABEL: v_clamp_dbg_use_src_f32:
160 ; SI: ; %bb.0:
161 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
162 ; SI-NEXT: s_mov_b32 s7, 0xf000
163 ; SI-NEXT: s_mov_b32 s6, 0
164 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
165 ; SI-NEXT: v_mov_b32_e32 v1, 0
166 ; SI-NEXT: s_waitcnt lgkmcnt(0)
167 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
168 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
169 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
170 ; SI-NEXT: s_waitcnt vmcnt(0)
171 ; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp
172 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
173 ; SI-NEXT: s_endpgm
174 ;
175 ; GFX8-LABEL: v_clamp_dbg_use_src_f32:
176 ; GFX8: ; %bb.0:
177 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
178 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
179 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
180 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
181 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
182 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
183 ; GFX8-NEXT: flat_load_dword v3, v[0:1]
184 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
185 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
186 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
187 ; GFX8-NEXT: s_waitcnt vmcnt(0)
188 ; GFX8-NEXT: v_add_f32_e64 v2, v3, 1.0 clamp
189 ; GFX8-NEXT: flat_store_dword v[0:1], v2
190 ; GFX8-NEXT: s_endpgm
191 ;
192 ; GFX9-LABEL: v_clamp_dbg_use_src_f32:
193 ; GFX9: ; %bb.0:
194 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
195 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
196 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
197 ; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
198 ; GFX9-NEXT: s_waitcnt vmcnt(0)
199 ; GFX9-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp
200 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
201 ; GFX9-NEXT: s_endpgm
202 ;
203 ; GFX11-LABEL: v_clamp_dbg_use_src_f32:
204 ; GFX11: ; %bb.0:
205 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
206 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
207 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
208 ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
209 ; GFX11-NEXT: s_waitcnt vmcnt(0)
210 ; GFX11-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp
211 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
212 ; GFX11-NEXT: s_nop 0
213 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
214 ; GFX11-NEXT: s_endpgm
215 %tid = call i32 @llvm.amdgcn.workitem.id.x()
216 %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
217 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
218 %a = load float, ptr addrspace(1) %gep0
219 %add = fadd float %a, 1.0
220 call void @llvm.dbg.value(metadata float %add, i64 0, metadata !4, metadata !9), !dbg !10
221 %max = call float @llvm.maxnum.f32(float %add, float 0.0)
222 %clamp = call float @llvm.minnum.f32(float %max, float 1.0)
223 store float %clamp, ptr addrspace(1) %out.gep
224 ret void
225 }
227 define amdgpu_kernel void @v_clamp_add_neg_src_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
228 ; SI-LABEL: v_clamp_add_neg_src_f32:
229 ; SI: ; %bb.0:
230 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
231 ; SI-NEXT: s_mov_b32 s7, 0xf000
232 ; SI-NEXT: s_mov_b32 s6, 0
233 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
234 ; SI-NEXT: v_mov_b32_e32 v1, 0
235 ; SI-NEXT: s_waitcnt lgkmcnt(0)
236 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
237 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
238 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
239 ; SI-NEXT: s_waitcnt vmcnt(0)
240 ; SI-NEXT: v_floor_f32_e32 v2, v2
241 ; SI-NEXT: v_max_f32_e64 v2, -v2, -v2 clamp
242 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
243 ; SI-NEXT: s_endpgm
244 ;
245 ; GFX8-LABEL: v_clamp_add_neg_src_f32:
246 ; GFX8: ; %bb.0:
247 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
248 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
249 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
250 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
251 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
252 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
253 ; GFX8-NEXT: flat_load_dword v3, v[0:1]
254 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
255 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
256 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
257 ; GFX8-NEXT: s_waitcnt vmcnt(0)
258 ; GFX8-NEXT: v_floor_f32_e32 v2, v3
259 ; GFX8-NEXT: v_max_f32_e64 v2, -v2, -v2 clamp
260 ; GFX8-NEXT: flat_store_dword v[0:1], v2
261 ; GFX8-NEXT: s_endpgm
262 ;
263 ; GFX9-LABEL: v_clamp_add_neg_src_f32:
264 ; GFX9: ; %bb.0:
265 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
266 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
267 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
268 ; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
269 ; GFX9-NEXT: s_waitcnt vmcnt(0)
270 ; GFX9-NEXT: v_floor_f32_e32 v1, v1
271 ; GFX9-NEXT: v_max_f32_e64 v1, -v1, -v1 clamp
272 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
273 ; GFX9-NEXT: s_endpgm
274 ;
275 ; GFX11-LABEL: v_clamp_add_neg_src_f32:
276 ; GFX11: ; %bb.0:
277 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
278 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
279 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
280 ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
281 ; GFX11-NEXT: s_waitcnt vmcnt(0)
282 ; GFX11-NEXT: v_floor_f32_e32 v1, v1
283 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
284 ; GFX11-NEXT: v_max_f32_e64 v1, -v1, -v1 clamp
285 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
286 ; GFX11-NEXT: s_nop 0
287 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
288 ; GFX11-NEXT: s_endpgm
289 %tid = call i32 @llvm.amdgcn.workitem.id.x()
290 %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
291 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
292 %a = load float, ptr addrspace(1) %gep0
293 %floor = call float @llvm.floor.f32(float %a)
294 %neg.floor = fneg float %floor
295 %max = call float @llvm.maxnum.f32(float %neg.floor, float 0.0)
296 %clamp = call float @llvm.minnum.f32(float %max, float 1.0)
297 store float %clamp, ptr addrspace(1) %out.gep
298 ret void
299 }
301 define amdgpu_kernel void @v_non_clamp_max_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
302 ; SI-LABEL: v_non_clamp_max_f32:
303 ; SI: ; %bb.0:
304 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
305 ; SI-NEXT: s_mov_b32 s7, 0xf000
306 ; SI-NEXT: s_mov_b32 s6, 0
307 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
308 ; SI-NEXT: v_mov_b32_e32 v1, 0
309 ; SI-NEXT: s_waitcnt lgkmcnt(0)
310 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
311 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
312 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
313 ; SI-NEXT: s_waitcnt vmcnt(0)
314 ; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
315 ; SI-NEXT: v_max_f32_e32 v2, 0, v2
316 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
317 ; SI-NEXT: s_endpgm
318 ;
319 ; GFX8-LABEL: v_non_clamp_max_f32:
320 ; GFX8: ; %bb.0:
321 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
322 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
323 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
324 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
325 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
326 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
327 ; GFX8-NEXT: flat_load_dword v3, v[0:1]
328 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
329 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
330 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
331 ; GFX8-NEXT: s_waitcnt vmcnt(0)
332 ; GFX8-NEXT: v_add_f32_e32 v2, 1.0, v3
333 ; GFX8-NEXT: v_max_f32_e32 v2, 0, v2
334 ; GFX8-NEXT: flat_store_dword v[0:1], v2
335 ; GFX8-NEXT: s_endpgm
336 ;
337 ; GFX9-LABEL: v_non_clamp_max_f32:
338 ; GFX9: ; %bb.0:
339 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
340 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
341 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
342 ; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
343 ; GFX9-NEXT: s_waitcnt vmcnt(0)
344 ; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
345 ; GFX9-NEXT: v_max_f32_e32 v1, 0, v1
346 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
347 ; GFX9-NEXT: s_endpgm
348 ;
349 ; GFX11-LABEL: v_non_clamp_max_f32:
350 ; GFX11: ; %bb.0:
351 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
352 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
353 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
354 ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
355 ; GFX11-NEXT: s_waitcnt vmcnt(0)
356 ; GFX11-NEXT: v_add_f32_e32 v1, 1.0, v1
357 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
358 ; GFX11-NEXT: v_max_f32_e32 v1, 0, v1
359 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
360 ; GFX11-NEXT: s_nop 0
361 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
362 ; GFX11-NEXT: s_endpgm
363 %tid = call i32 @llvm.amdgcn.workitem.id.x()
364 %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
365 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
366 %a = load float, ptr addrspace(1) %gep0
367 %add = fadd float %a, 1.0
368 %max = call float @llvm.maxnum.f32(float %add, float 0.0)
369 store float %max, ptr addrspace(1) %out.gep
370 ret void
371 }
373 define amdgpu_kernel void @v_clamp_add_src_f32_denormals(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #2 {
374 ; SI-LABEL: v_clamp_add_src_f32_denormals:
375 ; SI: ; %bb.0:
376 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
377 ; SI-NEXT: s_mov_b32 s7, 0xf000
378 ; SI-NEXT: s_mov_b32 s6, 0
379 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
380 ; SI-NEXT: v_mov_b32_e32 v1, 0
381 ; SI-NEXT: s_waitcnt lgkmcnt(0)
382 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
383 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
384 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
385 ; SI-NEXT: s_waitcnt vmcnt(0)
386 ; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp
387 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
388 ; SI-NEXT: s_endpgm
389 ;
390 ; GFX8-LABEL: v_clamp_add_src_f32_denormals:
391 ; GFX8: ; %bb.0:
392 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
393 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
394 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
395 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
396 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
397 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
398 ; GFX8-NEXT: flat_load_dword v3, v[0:1]
399 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
400 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
401 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
402 ; GFX8-NEXT: s_waitcnt vmcnt(0)
403 ; GFX8-NEXT: v_add_f32_e64 v2, v3, 1.0 clamp
404 ; GFX8-NEXT: flat_store_dword v[0:1], v2
405 ; GFX8-NEXT: s_endpgm
406 ;
407 ; GFX9-LABEL: v_clamp_add_src_f32_denormals:
408 ; GFX9: ; %bb.0:
409 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
410 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
411 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
412 ; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
413 ; GFX9-NEXT: s_waitcnt vmcnt(0)
414 ; GFX9-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp
415 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
416 ; GFX9-NEXT: s_endpgm
417 ;
418 ; GFX11-LABEL: v_clamp_add_src_f32_denormals:
419 ; GFX11: ; %bb.0:
420 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
421 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
422 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
423 ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
424 ; GFX11-NEXT: s_waitcnt vmcnt(0)
425 ; GFX11-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp
426 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
427 ; GFX11-NEXT: s_nop 0
428 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
429 ; GFX11-NEXT: s_endpgm
430 %tid = call i32 @llvm.amdgcn.workitem.id.x()
431 %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
432 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
433 %a = load float, ptr addrspace(1) %gep0
434 %add = fadd float %a, 1.0
435 %max = call float @llvm.maxnum.f32(float %add, float 0.0)
436 %clamp = call float @llvm.minnum.f32(float %max, float 1.0)
437 store float %clamp, ptr addrspace(1) %out.gep
438 ret void
439 }
441 define amdgpu_kernel void @v_clamp_add_src_f16_denorm(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
442 ; SI-LABEL: v_clamp_add_src_f16_denorm:
443 ; SI: ; %bb.0:
444 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
445 ; SI-NEXT: s_mov_b32 s7, 0xf000
446 ; SI-NEXT: s_mov_b32 s6, 0
447 ; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0
448 ; SI-NEXT: v_mov_b32_e32 v1, 0
449 ; SI-NEXT: s_waitcnt lgkmcnt(0)
450 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
451 ; SI-NEXT: buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64
452 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
453 ; SI-NEXT: s_waitcnt vmcnt(0)
454 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
455 ; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp
456 ; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
457 ; SI-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64
458 ; SI-NEXT: s_endpgm
459 ;
460 ; GFX8-LABEL: v_clamp_add_src_f16_denorm:
461 ; GFX8: ; %bb.0:
462 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
463 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 1, v0
464 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
465 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
466 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
467 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
468 ; GFX8-NEXT: flat_load_ushort v3, v[0:1]
469 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
470 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
471 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
472 ; GFX8-NEXT: s_waitcnt vmcnt(0)
473 ; GFX8-NEXT: v_add_f16_e64 v2, v3, 1.0 clamp
474 ; GFX8-NEXT: flat_store_short v[0:1], v2
475 ; GFX8-NEXT: s_endpgm
476 ;
477 ; GFX9-LABEL: v_clamp_add_src_f16_denorm:
478 ; GFX9: ; %bb.0:
479 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
480 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
481 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
482 ; GFX9-NEXT: global_load_ushort v1, v0, s[2:3]
483 ; GFX9-NEXT: s_waitcnt vmcnt(0)
484 ; GFX9-NEXT: v_add_f16_e64 v1, v1, 1.0 clamp
485 ; GFX9-NEXT: global_store_short v0, v1, s[0:1]
486 ; GFX9-NEXT: s_endpgm
487 ;
488 ; GFX11-LABEL: v_clamp_add_src_f16_denorm:
489 ; GFX11: ; %bb.0:
490 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
491 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0
492 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
493 ; GFX11-NEXT: global_load_u16 v1, v0, s[2:3]
494 ; GFX11-NEXT: s_waitcnt vmcnt(0)
495 ; GFX11-NEXT: v_add_f16_e64 v1, v1, 1.0 clamp
496 ; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
497 ; GFX11-NEXT: s_nop 0
498 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
499 ; GFX11-NEXT: s_endpgm
500 %tid = call i32 @llvm.amdgcn.workitem.id.x()
501 %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid
502 %out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid
503 %a = load half, ptr addrspace(1) %gep0
504 %add = fadd half %a, 1.0
505 %max = call half @llvm.maxnum.f16(half %add, half 0.0)
506 %clamp = call half @llvm.minnum.f16(half %max, half 1.0)
507 store half %clamp, ptr addrspace(1) %out.gep
508 ret void
509 }
511 define amdgpu_kernel void @v_clamp_add_src_f16_no_denormals(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #3 {
512 ; SI-LABEL: v_clamp_add_src_f16_no_denormals:
513 ; SI: ; %bb.0:
514 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
515 ; SI-NEXT: s_mov_b32 s7, 0xf000
516 ; SI-NEXT: s_mov_b32 s6, 0
517 ; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0
518 ; SI-NEXT: v_mov_b32_e32 v1, 0
519 ; SI-NEXT: s_waitcnt lgkmcnt(0)
520 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
521 ; SI-NEXT: buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64
522 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
523 ; SI-NEXT: s_waitcnt vmcnt(0)
524 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
525 ; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp
526 ; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
527 ; SI-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64
528 ; SI-NEXT: s_endpgm
529 ;
530 ; GFX8-LABEL: v_clamp_add_src_f16_no_denormals:
531 ; GFX8: ; %bb.0:
532 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
533 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 1, v0
534 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
535 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
536 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
537 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
538 ; GFX8-NEXT: flat_load_ushort v3, v[0:1]
539 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
540 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
541 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
542 ; GFX8-NEXT: s_waitcnt vmcnt(0)
543 ; GFX8-NEXT: v_add_f16_e64 v2, v3, 1.0 clamp
544 ; GFX8-NEXT: flat_store_short v[0:1], v2
545 ; GFX8-NEXT: s_endpgm
546 ;
547 ; GFX9-LABEL: v_clamp_add_src_f16_no_denormals:
548 ; GFX9: ; %bb.0:
549 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
550 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
551 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
552 ; GFX9-NEXT: global_load_ushort v1, v0, s[2:3]
553 ; GFX9-NEXT: s_waitcnt vmcnt(0)
554 ; GFX9-NEXT: v_add_f16_e64 v1, v1, 1.0 clamp
555 ; GFX9-NEXT: global_store_short v0, v1, s[0:1]
556 ; GFX9-NEXT: s_endpgm
557 ;
558 ; GFX11-LABEL: v_clamp_add_src_f16_no_denormals:
559 ; GFX11: ; %bb.0:
560 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
561 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0
562 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
563 ; GFX11-NEXT: global_load_u16 v1, v0, s[2:3]
564 ; GFX11-NEXT: s_waitcnt vmcnt(0)
565 ; GFX11-NEXT: v_add_f16_e64 v1, v1, 1.0 clamp
566 ; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
567 ; GFX11-NEXT: s_nop 0
568 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
569 ; GFX11-NEXT: s_endpgm
570 %tid = call i32 @llvm.amdgcn.workitem.id.x()
571 %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid
572 %out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid
573 %a = load half, ptr addrspace(1) %gep0
574 %add = fadd half %a, 1.0
575 %max = call half @llvm.maxnum.f16(half %add, half 0.0)
576 %clamp = call half @llvm.minnum.f16(half %max, half 1.0)
577 store half %clamp, ptr addrspace(1) %out.gep
578 ret void
579 }
581 define amdgpu_kernel void @v_clamp_add_src_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
582 ; SI-LABEL: v_clamp_add_src_v2f32:
583 ; SI: ; %bb.0:
584 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
585 ; SI-NEXT: s_mov_b32 s7, 0xf000
586 ; SI-NEXT: s_mov_b32 s6, 0
587 ; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
588 ; SI-NEXT: v_mov_b32_e32 v1, 0
589 ; SI-NEXT: s_waitcnt lgkmcnt(0)
590 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
591 ; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
592 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
593 ; SI-NEXT: s_waitcnt vmcnt(0)
594 ; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp
595 ; SI-NEXT: v_add_f32_e64 v3, v3, 1.0 clamp
596 ; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
597 ; SI-NEXT: s_endpgm
598 ;
599 ; GFX8-LABEL: v_clamp_add_src_v2f32:
600 ; GFX8: ; %bb.0:
601 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
602 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0
603 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
604 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
605 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
606 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
607 ; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
608 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
609 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v2
610 ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
611 ; GFX8-NEXT: s_waitcnt vmcnt(0)
612 ; GFX8-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp
613 ; GFX8-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp
614 ; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
615 ; GFX8-NEXT: s_endpgm
616 ;
617 ; GFX9-LABEL: v_clamp_add_src_v2f32:
618 ; GFX9: ; %bb.0:
619 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
620 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 3, v0
621 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
622 ; GFX9-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]
623 ; GFX9-NEXT: s_waitcnt vmcnt(0)
624 ; GFX9-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp
625 ; GFX9-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp
626 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
627 ; GFX9-NEXT: s_endpgm
628 ;
629 ; GFX11-LABEL: v_clamp_add_src_v2f32:
630 ; GFX11: ; %bb.0:
631 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
632 ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0
633 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
634 ; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3]
635 ; GFX11-NEXT: s_waitcnt vmcnt(0)
636 ; GFX11-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp
637 ; GFX11-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp
638 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
639 ; GFX11-NEXT: s_nop 0
640 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
641 ; GFX11-NEXT: s_endpgm
642 %tid = call i32 @llvm.amdgcn.workitem.id.x()
643 %gep0 = getelementptr <2 x float>, ptr addrspace(1) %aptr, i32 %tid
644 %out.gep = getelementptr <2 x float>, ptr addrspace(1) %out, i32 %tid
645 %a = load <2 x float>, ptr addrspace(1) %gep0
646 %add = fadd <2 x float> %a, <float 1.0, float 1.0>
647 %max = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %add, <2 x float> zeroinitializer)
648 %clamp = call <2 x float> @llvm.minnum.v2f32(<2 x float> %max, <2 x float> <float 1.0, float 1.0>)
649 store <2 x float> %clamp, ptr addrspace(1) %out.gep
650 ret void
651 }
653 define amdgpu_kernel void @v_clamp_add_src_f64(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
654 ; SI-LABEL: v_clamp_add_src_f64:
655 ; SI: ; %bb.0:
656 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
657 ; SI-NEXT: s_mov_b32 s7, 0xf000
658 ; SI-NEXT: s_mov_b32 s6, 0
659 ; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
660 ; SI-NEXT: v_mov_b32_e32 v1, 0
661 ; SI-NEXT: s_waitcnt lgkmcnt(0)
662 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
663 ; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
664 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
665 ; SI-NEXT: s_waitcnt vmcnt(0)
666 ; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 clamp
667 ; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
668 ; SI-NEXT: s_endpgm
669 ;
670 ; GFX8-LABEL: v_clamp_add_src_f64:
671 ; GFX8: ; %bb.0:
672 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
673 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0
674 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
675 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
676 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
677 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
678 ; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
679 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
680 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v2
681 ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
682 ; GFX8-NEXT: s_waitcnt vmcnt(0)
683 ; GFX8-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 clamp
684 ; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
685 ; GFX8-NEXT: s_endpgm
686 ;
687 ; GFX9-LABEL: v_clamp_add_src_f64:
688 ; GFX9: ; %bb.0:
689 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
690 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 3, v0
691 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
692 ; GFX9-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]
693 ; GFX9-NEXT: s_waitcnt vmcnt(0)
694 ; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 clamp
695 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
696 ; GFX9-NEXT: s_endpgm
697 ;
698 ; GFX11-LABEL: v_clamp_add_src_f64:
699 ; GFX11: ; %bb.0:
700 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
701 ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0
702 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
703 ; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3]
704 ; GFX11-NEXT: s_waitcnt vmcnt(0)
705 ; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 clamp
706 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
707 ; GFX11-NEXT: s_nop 0
708 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
709 ; GFX11-NEXT: s_endpgm
710 %tid = call i32 @llvm.amdgcn.workitem.id.x()
711 %gep0 = getelementptr double, ptr addrspace(1) %aptr, i32 %tid
712 %out.gep = getelementptr double, ptr addrspace(1) %out, i32 %tid
713 %a = load double, ptr addrspace(1) %gep0
714 %add = fadd double %a, 1.0
715 %max = call double @llvm.maxnum.f64(double %add, double 0.0)
716 %clamp = call double @llvm.minnum.f64(double %max, double 1.0)
717 store double %clamp, ptr addrspace(1) %out.gep
718 ret void
719 }
721 define amdgpu_kernel void @v_clamp_mac_to_mad(ptr addrspace(1) %out, ptr addrspace(1) %aptr, float %a) #0 {
722 ; SI-LABEL: v_clamp_mac_to_mad:
723 ; SI: ; %bb.0:
724 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
725 ; SI-NEXT: s_load_dword s8, s[0:1], 0xd
726 ; SI-NEXT: s_mov_b32 s3, 0xf000
727 ; SI-NEXT: s_mov_b32 s2, 0
728 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
729 ; SI-NEXT: s_waitcnt lgkmcnt(0)
730 ; SI-NEXT: s_mov_b64 s[0:1], s[6:7]
731 ; SI-NEXT: v_mov_b32_e32 v1, 0
732 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
733 ; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
734 ; SI-NEXT: s_waitcnt vmcnt(0)
735 ; SI-NEXT: v_mad_f32 v3, s8, s8, v2 clamp
736 ; SI-NEXT: v_add_f32_e32 v2, v3, v2
737 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
738 ; SI-NEXT: s_endpgm
739 ;
740 ; GFX8-LABEL: v_clamp_mac_to_mad:
741 ; GFX8: ; %bb.0:
742 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
743 ; GFX8-NEXT: s_load_dword s0, s[0:1], 0x34
744 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
745 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
746 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
747 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
748 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
749 ; GFX8-NEXT: flat_load_dword v3, v[0:1]
750 ; GFX8-NEXT: v_mov_b32_e32 v1, s5
751 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
752 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
753 ; GFX8-NEXT: s_waitcnt vmcnt(0)
754 ; GFX8-NEXT: v_mad_f32 v2, s0, s0, v3 clamp
755 ; GFX8-NEXT: v_add_f32_e32 v2, v2, v3
756 ; GFX8-NEXT: flat_store_dword v[0:1], v2
757 ; GFX8-NEXT: s_endpgm
758 ;
759 ; GFX9-LABEL: v_clamp_mac_to_mad:
760 ; GFX9: ; %bb.0:
761 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
762 ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x34
763 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
764 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
765 ; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
766 ; GFX9-NEXT: s_waitcnt vmcnt(0)
767 ; GFX9-NEXT: v_mad_f32 v2, s2, s2, v1 clamp
768 ; GFX9-NEXT: v_add_f32_e32 v1, v2, v1
769 ; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
770 ; GFX9-NEXT: s_endpgm
771 ;
772 ; GFX11-LABEL: v_clamp_mac_to_mad:
773 ; GFX11: ; %bb.0:
774 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
775 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
776 ; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x34
777 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
778 ; GFX11-NEXT: global_load_b32 v1, v0, s[6:7]
779 ; GFX11-NEXT: v_mul_f32_e64 v2, s0, s0
780 ; GFX11-NEXT: s_waitcnt vmcnt(0)
781 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
782 ; GFX11-NEXT: v_add_f32_e64 v2, v2, v1 clamp
783 ; GFX11-NEXT: v_add_f32_e32 v1, v2, v1
784 ; GFX11-NEXT: global_store_b32 v0, v1, s[4:5]
785 ; GFX11-NEXT: s_nop 0
786 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
787 ; GFX11-NEXT: s_endpgm
788 %tid = call i32 @llvm.amdgcn.workitem.id.x()
789 %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
790 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
791 %b = load float, ptr addrspace(1) %gep0
793 %mul = fmul float %a, %a
794 %add = fadd float %mul, %b
795 %max = call float @llvm.maxnum.f32(float %add, float 0.0)
796 %clamp = call float @llvm.minnum.f32(float %max, float 1.0)
797 %res = fadd float %clamp, %b
798 store float %res, ptr addrspace(1) %out.gep
799 ret void
800 }
802 define amdgpu_kernel void @v_clamp_add_src_v2f16_denorm(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
803 ; SI-LABEL: v_clamp_add_src_v2f16_denorm:
804 ; SI: ; %bb.0:
805 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
806 ; SI-NEXT: s_mov_b32 s7, 0xf000
807 ; SI-NEXT: s_mov_b32 s6, 0
808 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
809 ; SI-NEXT: v_mov_b32_e32 v1, 0
810 ; SI-NEXT: s_waitcnt lgkmcnt(0)
811 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
812 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
813 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
814 ; SI-NEXT: s_waitcnt vmcnt(0)
815 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
816 ; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
817 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
818 ; SI-NEXT: v_add_f32_e64 v3, v3, 1.0 clamp
819 ; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp
820 ; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
821 ; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
822 ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
823 ; SI-NEXT: v_or_b32_e32 v2, v2, v3
824 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
825 ; SI-NEXT: s_endpgm
826 ;
827 ; GFX8-LABEL: v_clamp_add_src_v2f16_denorm:
828 ; GFX8: ; %bb.0:
829 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
830 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
831 ; GFX8-NEXT: v_mov_b32_e32 v4, 0x3c00
832 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
833 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
834 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
835 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
836 ; GFX8-NEXT: flat_load_dword v3, v[0:1]
837 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
838 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
839 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
840 ; GFX8-NEXT: s_waitcnt vmcnt(0)
841 ; GFX8-NEXT: v_add_f16_e64 v2, v3, 1.0 clamp
842 ; GFX8-NEXT: v_add_f16_sdwa v3, v3, v4 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
843 ; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
844 ; GFX8-NEXT: flat_store_dword v[0:1], v2
845 ; GFX8-NEXT: s_endpgm
846 ;
847 ; GFX9-LABEL: v_clamp_add_src_v2f16_denorm:
848 ; GFX9: ; %bb.0:
849 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
850 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
851 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
852 ; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
853 ; GFX9-NEXT: s_waitcnt vmcnt(0)
854 ; GFX9-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0] clamp
855 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
856 ; GFX9-NEXT: s_endpgm
857 ;
858 ; GFX11-LABEL: v_clamp_add_src_v2f16_denorm:
859 ; GFX11: ; %bb.0:
860 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
861 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
862 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
863 ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
864 ; GFX11-NEXT: s_waitcnt vmcnt(0)
865 ; GFX11-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0] clamp
866 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
867 ; GFX11-NEXT: s_nop 0
868 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
869 ; GFX11-NEXT: s_endpgm
870 %tid = call i32 @llvm.amdgcn.workitem.id.x()
871 %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
872 %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
873 %a = load <2 x half>, ptr addrspace(1) %gep0
874 %add = fadd <2 x half> %a, <half 1.0, half 1.0>
875 %max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %add, <2 x half> zeroinitializer)
876 %clamp = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half 1.0>)
877 store <2 x half> %clamp, ptr addrspace(1) %out.gep
878 ret void
879 }
881 define amdgpu_kernel void @v_clamp_add_src_v2f16_no_denormals(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #3 {
882 ; SI-LABEL: v_clamp_add_src_v2f16_no_denormals:
883 ; SI: ; %bb.0:
884 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
885 ; SI-NEXT: s_mov_b32 s7, 0xf000
886 ; SI-NEXT: s_mov_b32 s6, 0
887 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
888 ; SI-NEXT: v_mov_b32_e32 v1, 0
889 ; SI-NEXT: s_waitcnt lgkmcnt(0)
890 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
891 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
892 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
893 ; SI-NEXT: s_waitcnt vmcnt(0)
894 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
895 ; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
896 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
897 ; SI-NEXT: v_add_f32_e64 v3, v3, 1.0 clamp
898 ; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp
899 ; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
900 ; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
901 ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
902 ; SI-NEXT: v_or_b32_e32 v2, v2, v3
903 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
904 ; SI-NEXT: s_endpgm
905 ;
906 ; GFX8-LABEL: v_clamp_add_src_v2f16_no_denormals:
907 ; GFX8: ; %bb.0:
908 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
909 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
910 ; GFX8-NEXT: v_mov_b32_e32 v4, 0x3c00
911 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
912 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
913 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
914 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
915 ; GFX8-NEXT: flat_load_dword v3, v[0:1]
916 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
917 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
918 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
919 ; GFX8-NEXT: s_waitcnt vmcnt(0)
920 ; GFX8-NEXT: v_add_f16_e64 v2, v3, 1.0 clamp
921 ; GFX8-NEXT: v_add_f16_sdwa v3, v3, v4 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
922 ; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
923 ; GFX8-NEXT: flat_store_dword v[0:1], v2
924 ; GFX8-NEXT: s_endpgm
925 ;
926 ; GFX9-LABEL: v_clamp_add_src_v2f16_no_denormals:
927 ; GFX9: ; %bb.0:
928 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
929 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
930 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
931 ; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
932 ; GFX9-NEXT: s_waitcnt vmcnt(0)
933 ; GFX9-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0] clamp
934 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
935 ; GFX9-NEXT: s_endpgm
936 ;
937 ; GFX11-LABEL: v_clamp_add_src_v2f16_no_denormals:
938 ; GFX11: ; %bb.0:
939 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
940 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
941 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
942 ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
943 ; GFX11-NEXT: s_waitcnt vmcnt(0)
944 ; GFX11-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0] clamp
945 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
946 ; GFX11-NEXT: s_nop 0
947 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
948 ; GFX11-NEXT: s_endpgm
949 %tid = call i32 @llvm.amdgcn.workitem.id.x()
950 %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
951 %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
952 %a = load <2 x half>, ptr addrspace(1) %gep0
953 %add = fadd <2 x half> %a, <half 1.0, half 1.0>
954 %max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %add, <2 x half> zeroinitializer)
955 %clamp = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half 1.0>)
956 store <2 x half> %clamp, ptr addrspace(1) %out.gep
957 ret void
958 }
960 define amdgpu_kernel void @v_clamp_add_src_v2f16_denorm_neg(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
961 ; SI-LABEL: v_clamp_add_src_v2f16_denorm_neg:
962 ; SI: ; %bb.0:
963 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
964 ; SI-NEXT: s_mov_b32 s7, 0xf000
965 ; SI-NEXT: s_mov_b32 s6, 0
966 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
967 ; SI-NEXT: v_mov_b32_e32 v1, 0
968 ; SI-NEXT: s_waitcnt lgkmcnt(0)
969 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
970 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
971 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
972 ; SI-NEXT: s_waitcnt vmcnt(0)
973 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
974 ; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
975 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
976 ; SI-NEXT: v_add_f32_e32 v3, 1.0, v3
977 ; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
978 ; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
979 ; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
980 ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
981 ; SI-NEXT: v_or_b32_e32 v2, v2, v3
982 ; SI-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
983 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
984 ; SI-NEXT: v_cvt_f32_f16_e64 v3, v3 clamp
985 ; SI-NEXT: v_cvt_f32_f16_e64 v2, v2 clamp
986 ; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
987 ; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
988 ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
989 ; SI-NEXT: v_or_b32_e32 v2, v2, v3
990 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
991 ; SI-NEXT: s_endpgm
992 ;
993 ; GFX8-LABEL: v_clamp_add_src_v2f16_denorm_neg:
994 ; GFX8: ; %bb.0:
995 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
996 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
997 ; GFX8-NEXT: v_mov_b32_e32 v4, 0x3c00
998 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
999 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
1000 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
1001 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
1002 ; GFX8-NEXT: flat_load_dword v3, v[0:1]
1003 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
1004 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
1005 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
1006 ; GFX8-NEXT: s_waitcnt vmcnt(0)
1007 ; GFX8-NEXT: v_add_f16_e32 v2, 1.0, v3
1008 ; GFX8-NEXT: v_add_f16_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1009 ; GFX8-NEXT: v_max_f16_sdwa v3, -v3, -v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
1010 ; GFX8-NEXT: v_max_f16_e64 v2, -v2, -v2 clamp
1011 ; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
1012 ; GFX8-NEXT: flat_store_dword v[0:1], v2
1013 ; GFX8-NEXT: s_endpgm
1014 ;
1015 ; GFX9-LABEL: v_clamp_add_src_v2f16_denorm_neg:
1016 ; GFX9: ; %bb.0:
1017 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1018 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1019 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1020 ; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
1021 ; GFX9-NEXT: s_waitcnt vmcnt(0)
1022 ; GFX9-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0]
1023 ; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 neg_lo:[1,1] neg_hi:[1,1] clamp
1024 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
1025 ; GFX9-NEXT: s_endpgm
1026 ;
1027 ; GFX11-LABEL: v_clamp_add_src_v2f16_denorm_neg:
1028 ; GFX11: ; %bb.0:
1029 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1030 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1031 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1032 ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
1033 ; GFX11-NEXT: s_waitcnt vmcnt(0)
1034 ; GFX11-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0]
1035 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1036 ; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 neg_lo:[1,1] neg_hi:[1,1] clamp
1037 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1038 ; GFX11-NEXT: s_nop 0
1039 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1040 ; GFX11-NEXT: s_endpgm
1041 %tid = call i32 @llvm.amdgcn.workitem.id.x()
1042 %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
1043 %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
1044 %a = load <2 x half>, ptr addrspace(1) %gep0
1045 %add = fadd <2 x half> %a, <half 1.0, half 1.0>
1046 %neg.add = fsub <2 x half> <half -0.0, half -0.0>, %add
1047 %max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %neg.add, <2 x half> zeroinitializer)
1048 %clamp = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half 1.0>)
1049 store <2 x half> %clamp, ptr addrspace(1) %out.gep
1050 ret void
1051 }
1053 define amdgpu_kernel void @v_clamp_add_src_v2f16_denorm_neg_lo(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
1054 ; SI-LABEL: v_clamp_add_src_v2f16_denorm_neg_lo:
1055 ; SI: ; %bb.0:
1056 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1057 ; SI-NEXT: s_mov_b32 s7, 0xf000
1058 ; SI-NEXT: s_mov_b32 s6, 0
1059 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1060 ; SI-NEXT: v_mov_b32_e32 v1, 0
1061 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1062 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
1063 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
1064 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
1065 ; SI-NEXT: s_waitcnt vmcnt(0)
1066 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
1067 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
1068 ; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
1069 ; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
1070 ; SI-NEXT: v_add_f32_e64 v3, v3, 1.0 clamp
1071 ; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
1072 ; SI-NEXT: v_max_f32_e64 v2, -v2, -v2 clamp
1073 ; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
1074 ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
1075 ; SI-NEXT: v_or_b32_e32 v2, v2, v3
1076 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
1077 ; SI-NEXT: s_endpgm
1078 ;
1079 ; GFX8-LABEL: v_clamp_add_src_v2f16_denorm_neg_lo:
1080 ; GFX8: ; %bb.0:
1081 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1082 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
1083 ; GFX8-NEXT: v_mov_b32_e32 v4, 0x3c00
1084 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
1085 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
1086 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
1087 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
1088 ; GFX8-NEXT: flat_load_dword v3, v[0:1]
1089 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
1090 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
1091 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
1092 ; GFX8-NEXT: s_waitcnt vmcnt(0)
1093 ; GFX8-NEXT: v_add_f16_e32 v2, 1.0, v3
1094 ; GFX8-NEXT: v_add_f16_sdwa v3, v3, v4 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1095 ; GFX8-NEXT: v_max_f16_e64 v2, -v2, -v2 clamp
1096 ; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
1097 ; GFX8-NEXT: flat_store_dword v[0:1], v2
1098 ; GFX8-NEXT: s_endpgm
1099 ;
1100 ; GFX9-LABEL: v_clamp_add_src_v2f16_denorm_neg_lo:
1101 ; GFX9: ; %bb.0:
1102 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1103 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1104 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1105 ; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
1106 ; GFX9-NEXT: s_waitcnt vmcnt(0)
1107 ; GFX9-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0]
1108 ; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 neg_lo:[1,1] clamp
1109 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
1110 ; GFX9-NEXT: s_endpgm
1111 ;
1112 ; GFX11-LABEL: v_clamp_add_src_v2f16_denorm_neg_lo:
1113 ; GFX11: ; %bb.0:
1114 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1115 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1116 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1117 ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
1118 ; GFX11-NEXT: s_waitcnt vmcnt(0)
1119 ; GFX11-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0]
1120 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1121 ; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 neg_lo:[1,1] clamp
1122 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1123 ; GFX11-NEXT: s_nop 0
1124 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1125 ; GFX11-NEXT: s_endpgm
1126 %tid = call i32 @llvm.amdgcn.workitem.id.x()
1127 %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
1128 %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
1129 %a = load <2 x half>, ptr addrspace(1) %gep0
1130 %add = fadd <2 x half> %a, <half 1.0, half 1.0>
1131 %lo = extractelement <2 x half> %add, i32 0
1132 %neg.lo = fsub half -0.0, %lo
1133 %neg.lo.add = insertelement <2 x half> %add, half %neg.lo, i32 0
1134 %max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %neg.lo.add, <2 x half> zeroinitializer)
1135 %clamp = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half 1.0>)
1136 store <2 x half> %clamp, ptr addrspace(1) %out.gep
1137 ret void
1138 }
1140 define amdgpu_kernel void @v_clamp_add_src_v2f16_denorm_neg_hi(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
1141 ; SI-LABEL: v_clamp_add_src_v2f16_denorm_neg_hi:
1142 ; SI: ; %bb.0:
1143 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1144 ; SI-NEXT: s_mov_b32 s7, 0xf000
1145 ; SI-NEXT: s_mov_b32 s6, 0
1146 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1147 ; SI-NEXT: v_mov_b32_e32 v1, 0
1148 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1149 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
1150 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
1151 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
1152 ; SI-NEXT: s_waitcnt vmcnt(0)
1153 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
1154 ; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
1155 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
1156 ; SI-NEXT: v_add_f32_e32 v3, 1.0, v3
1157 ; SI-NEXT: v_max_f32_e64 v3, -v3, -v3 clamp
1158 ; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp
1159 ; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
1160 ; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
1161 ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
1162 ; SI-NEXT: v_or_b32_e32 v2, v2, v3
1163 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
1164 ; SI-NEXT: s_endpgm
1165 ;
1166 ; GFX8-LABEL: v_clamp_add_src_v2f16_denorm_neg_hi:
1167 ; GFX8: ; %bb.0:
1168 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1169 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
1170 ; GFX8-NEXT: v_mov_b32_e32 v4, 0x3c00
1171 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
1172 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
1173 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
1174 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
1175 ; GFX8-NEXT: flat_load_dword v3, v[0:1]
1176 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
1177 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
1178 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
1179 ; GFX8-NEXT: s_waitcnt vmcnt(0)
1180 ; GFX8-NEXT: v_add_f16_e64 v2, v3, 1.0 clamp
1181 ; GFX8-NEXT: v_add_f16_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1182 ; GFX8-NEXT: v_max_f16_sdwa v3, -v3, -v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
1183 ; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
1184 ; GFX8-NEXT: flat_store_dword v[0:1], v2
1185 ; GFX8-NEXT: s_endpgm
1186 ;
1187 ; GFX9-LABEL: v_clamp_add_src_v2f16_denorm_neg_hi:
1188 ; GFX9: ; %bb.0:
1189 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1190 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1191 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1192 ; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
1193 ; GFX9-NEXT: s_waitcnt vmcnt(0)
1194 ; GFX9-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0]
1195 ; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 neg_hi:[1,1] clamp
1196 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
1197 ; GFX9-NEXT: s_endpgm
1198 ;
1199 ; GFX11-LABEL: v_clamp_add_src_v2f16_denorm_neg_hi:
1200 ; GFX11: ; %bb.0:
1201 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1202 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1203 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1204 ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
1205 ; GFX11-NEXT: s_waitcnt vmcnt(0)
1206 ; GFX11-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0]
1207 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1208 ; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 neg_hi:[1,1] clamp
1209 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1210 ; GFX11-NEXT: s_nop 0
1211 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1212 ; GFX11-NEXT: s_endpgm
1213 %tid = call i32 @llvm.amdgcn.workitem.id.x()
1214 %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
1215 %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
1216 %a = load <2 x half>, ptr addrspace(1) %gep0
1217 %add = fadd <2 x half> %a, <half 1.0, half 1.0>
1218 %hi = extractelement <2 x half> %add, i32 1
1219 %neg.hi = fsub half -0.0, %hi
1220 %neg.hi.add = insertelement <2 x half> %add, half %neg.hi, i32 1
1221 %max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %neg.hi.add, <2 x half> zeroinitializer)
1222 %clamp = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half 1.0>)
1223 store <2 x half> %clamp, ptr addrspace(1) %out.gep
1224 ret void
1225 }
1227 define amdgpu_kernel void @v_clamp_add_src_v2f16_denorm_shuf(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
1228 ; SI-LABEL: v_clamp_add_src_v2f16_denorm_shuf:
1229 ; SI: ; %bb.0:
1230 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1231 ; SI-NEXT: s_mov_b32 s7, 0xf000
1232 ; SI-NEXT: s_mov_b32 s6, 0
1233 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1234 ; SI-NEXT: v_mov_b32_e32 v1, 0
1235 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1236 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
1237 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
1238 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
1239 ; SI-NEXT: s_waitcnt vmcnt(0)
1240 ; SI-NEXT: v_cvt_f32_f16_e32 v3, v2
1241 ; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
1242 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
1243 ; SI-NEXT: v_add_f32_e64 v3, v3, 1.0 clamp
1244 ; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
1245 ; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp
1246 ; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
1247 ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
1248 ; SI-NEXT: v_or_b32_e32 v2, v2, v3
1249 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
1250 ; SI-NEXT: s_endpgm
1251 ;
1252 ; GFX8-LABEL: v_clamp_add_src_v2f16_denorm_shuf:
1253 ; GFX8: ; %bb.0:
1254 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1255 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
1256 ; GFX8-NEXT: v_mov_b32_e32 v4, 0x3c00
1257 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
1258 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
1259 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
1260 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
1261 ; GFX8-NEXT: flat_load_dword v3, v[0:1]
1262 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
1263 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
1264 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
1265 ; GFX8-NEXT: s_waitcnt vmcnt(0)
1266 ; GFX8-NEXT: v_add_f16_sdwa v2, v3, v4 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1267 ; GFX8-NEXT: v_add_f16_sdwa v3, v3, v4 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
1268 ; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
1269 ; GFX8-NEXT: flat_store_dword v[0:1], v2
1270 ; GFX8-NEXT: s_endpgm
1271 ;
1272 ; GFX9-LABEL: v_clamp_add_src_v2f16_denorm_shuf:
1273 ; GFX9: ; %bb.0:
1274 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1275 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1276 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1277 ; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
1278 ; GFX9-NEXT: s_waitcnt vmcnt(0)
1279 ; GFX9-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0]
1280 ; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 op_sel:[1,1] op_sel_hi:[0,0] clamp
1281 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
1282 ; GFX9-NEXT: s_endpgm
1283 ;
1284 ; GFX11-LABEL: v_clamp_add_src_v2f16_denorm_shuf:
1285 ; GFX11: ; %bb.0:
1286 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1287 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1288 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1289 ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
1290 ; GFX11-NEXT: s_waitcnt vmcnt(0)
1291 ; GFX11-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0]
1292 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1293 ; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 op_sel:[1,1] op_sel_hi:[0,0] clamp
1294 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1295 ; GFX11-NEXT: s_nop 0
1296 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1297 ; GFX11-NEXT: s_endpgm
1298 %tid = call i32 @llvm.amdgcn.workitem.id.x()
1299 %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
1300 %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
1301 %a = load <2 x half>, ptr addrspace(1) %gep0
1302 %add = fadd <2 x half> %a, <half 1.0, half 1.0>
1303 %shuf = shufflevector <2 x half> %add, <2 x half> undef, <2 x i32> <i32 1, i32 0>
1305 %max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %shuf, <2 x half> zeroinitializer)
1306 %clamp = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half 1.0>)
1307 store <2 x half> %clamp, ptr addrspace(1) %out.gep
1308 ret void
1309 }
1311 define amdgpu_kernel void @v_no_clamp_add_src_v2f16_f32_src(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
1312 ; SI-LABEL: v_no_clamp_add_src_v2f16_f32_src:
1313 ; SI: ; %bb.0:
1314 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1315 ; SI-NEXT: s_mov_b32 s7, 0xf000
1316 ; SI-NEXT: s_mov_b32 s6, 0
1317 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1318 ; SI-NEXT: v_mov_b32_e32 v1, 0
1319 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1320 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
1321 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
1322 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
1323 ; SI-NEXT: s_waitcnt vmcnt(0)
1324 ; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
1325 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
1326 ; SI-NEXT: v_cvt_f32_f16_e64 v3, v3 clamp
1327 ; SI-NEXT: v_cvt_f32_f16_e64 v2, v2 clamp
1328 ; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
1329 ; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
1330 ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
1331 ; SI-NEXT: v_or_b32_e32 v2, v2, v3
1332 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
1333 ; SI-NEXT: s_endpgm
1334 ;
1335 ; GFX8-LABEL: v_no_clamp_add_src_v2f16_f32_src:
1336 ; GFX8: ; %bb.0:
1337 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1338 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
1339 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
1340 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
1341 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
1342 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
1343 ; GFX8-NEXT: flat_load_dword v3, v[0:1]
1344 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
1345 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
1346 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
1347 ; GFX8-NEXT: s_waitcnt vmcnt(0)
1348 ; GFX8-NEXT: v_add_f32_e32 v2, 1.0, v3
1349 ; GFX8-NEXT: v_max_f16_sdwa v3, v2, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
1350 ; GFX8-NEXT: v_max_f16_e64 v2, v2, v2 clamp
1351 ; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
1352 ; GFX8-NEXT: flat_store_dword v[0:1], v2
1353 ; GFX8-NEXT: s_endpgm
1354 ;
1355 ; GFX9-LABEL: v_no_clamp_add_src_v2f16_f32_src:
1356 ; GFX9: ; %bb.0:
1357 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1358 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1359 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1360 ; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
1361 ; GFX9-NEXT: s_waitcnt vmcnt(0)
1362 ; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
1363 ; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 clamp
1364 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
1365 ; GFX9-NEXT: s_endpgm
1366 ;
1367 ; GFX11-LABEL: v_no_clamp_add_src_v2f16_f32_src:
1368 ; GFX11: ; %bb.0:
1369 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1370 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1371 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1372 ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
1373 ; GFX11-NEXT: s_waitcnt vmcnt(0)
1374 ; GFX11-NEXT: v_add_f32_e32 v1, 1.0, v1
1375 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1376 ; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 clamp
1377 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1378 ; GFX11-NEXT: s_nop 0
1379 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1380 ; GFX11-NEXT: s_endpgm
1381 %tid = call i32 @llvm.amdgcn.workitem.id.x()
1382 %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
1383 %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
1384 %a = load <2 x half>, ptr addrspace(1) %gep0
1385 %bc = bitcast <2 x half> %a to float
1386 %f32.op = fadd float %bc, 1.0
1387 %f32.op.cast = bitcast float %f32.op to <2 x half>
1388 %max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %f32.op.cast, <2 x half> zeroinitializer)
1389 %clamp = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half 1.0>)
1390 store <2 x half> %clamp, ptr addrspace(1) %out.gep
1391 ret void
1392 }
1394 define amdgpu_kernel void @v_no_clamp_add_packed_src_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
1395 ; SI-LABEL: v_no_clamp_add_packed_src_f32:
1396 ; SI: ; %bb.0:
1397 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1398 ; SI-NEXT: s_mov_b32 s7, 0xf000
1399 ; SI-NEXT: s_mov_b32 s6, 0
1400 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1401 ; SI-NEXT: v_mov_b32_e32 v1, 0
1402 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1403 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
1404 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
1405 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
1406 ; SI-NEXT: s_waitcnt vmcnt(0)
1407 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
1408 ; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
1409 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
1410 ; SI-NEXT: v_add_f32_e32 v3, 1.0, v3
1411 ; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
1412 ; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
1413 ; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
1414 ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
1415 ; SI-NEXT: v_or_b32_e32 v2, v2, v3
1416 ; SI-NEXT: v_max_f32_e64 v2, v2, v2 clamp
1417 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
1418 ; SI-NEXT: s_endpgm
1419 ;
1420 ; GFX8-LABEL: v_no_clamp_add_packed_src_f32:
1421 ; GFX8: ; %bb.0:
1422 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1423 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
1424 ; GFX8-NEXT: v_mov_b32_e32 v4, 0x3c00
1425 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
1426 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
1427 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
1428 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
1429 ; GFX8-NEXT: flat_load_dword v3, v[0:1]
1430 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
1431 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
1432 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
1433 ; GFX8-NEXT: s_waitcnt vmcnt(0)
1434 ; GFX8-NEXT: v_add_f16_sdwa v2, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1435 ; GFX8-NEXT: v_add_f16_e32 v3, 1.0, v3
1436 ; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
1437 ; GFX8-NEXT: v_max_f32_e64 v2, v2, v2 clamp
1438 ; GFX8-NEXT: flat_store_dword v[0:1], v2
1439 ; GFX8-NEXT: s_endpgm
1440 ;
1441 ; GFX9-LABEL: v_no_clamp_add_packed_src_f32:
1442 ; GFX9: ; %bb.0:
1443 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1444 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1445 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1446 ; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
1447 ; GFX9-NEXT: s_waitcnt vmcnt(0)
1448 ; GFX9-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0]
1449 ; GFX9-NEXT: v_max_f32_e64 v1, v1, v1 clamp
1450 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
1451 ; GFX9-NEXT: s_endpgm
1452 ;
1453 ; GFX11-LABEL: v_no_clamp_add_packed_src_f32:
1454 ; GFX11: ; %bb.0:
1455 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1456 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1457 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1458 ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
1459 ; GFX11-NEXT: s_waitcnt vmcnt(0)
1460 ; GFX11-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0]
1461 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1462 ; GFX11-NEXT: v_max_f32_e64 v1, v1, v1 clamp
1463 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1464 ; GFX11-NEXT: s_nop 0
1465 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1466 ; GFX11-NEXT: s_endpgm
1467 %tid = call i32 @llvm.amdgcn.workitem.id.x()
1468 %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid
1469 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
1470 %a = load <2 x half>, ptr addrspace(1) %gep0
1471 %add = fadd <2 x half> %a, <half 1.0, half 1.0>
1472 %bc.add = bitcast <2 x half> %add to float
1473 %max = call float @llvm.maxnum.f32(float %bc.add, float 0.0)
1474 %clamp = call float @llvm.minnum.f32(float %max, float 1.0)
1475 store float %clamp, ptr addrspace(1) %out.gep
1476 ret void
1477 }
1479 ; Since the high bits are zeroed, it probably would be OK in this case
1480 ; to use clamp.
1481 define amdgpu_kernel void @v_no_clamp_add_src_v2f16_f16_src(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
1482 ; SI-LABEL: v_no_clamp_add_src_v2f16_f16_src:
1483 ; SI: ; %bb.0:
1484 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1485 ; SI-NEXT: s_mov_b32 s7, 0xf000
1486 ; SI-NEXT: s_mov_b32 s6, 0
1487 ; SI-NEXT: v_lshlrev_b32_e32 v1, 1, v0
1488 ; SI-NEXT: v_mov_b32_e32 v2, 0
1489 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1490 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
1491 ; SI-NEXT: buffer_load_ushort v1, v[1:2], s[4:7], 0 addr64
1492 ; SI-NEXT: v_cvt_f32_f16_e64 v3, s6 clamp
1493 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
1494 ; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
1495 ; SI-NEXT: s_waitcnt vmcnt(0)
1496 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
1497 ; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
1498 ; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
1499 ; SI-NEXT: v_cvt_f32_f16_e64 v1, v1 clamp
1500 ; SI-NEXT: v_cvt_f16_f32_e32 v4, v1
1501 ; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
1502 ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v3
1503 ; SI-NEXT: v_or_b32_e32 v0, v4, v0
1504 ; SI-NEXT: buffer_store_dword v0, v[1:2], s[0:3], 0 addr64
1505 ; SI-NEXT: s_endpgm
1506 ;
1507 ; GFX8-LABEL: v_no_clamp_add_src_v2f16_f16_src:
1508 ; GFX8: ; %bb.0:
1509 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1510 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 1, v0
1511 ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1512 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
1513 ; GFX8-NEXT: v_mov_b32_e32 v2, s3
1514 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, s2, v1
1515 ; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
1516 ; GFX8-NEXT: flat_load_ushort v2, v[1:2]
1517 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
1518 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
1519 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
1520 ; GFX8-NEXT: s_waitcnt vmcnt(0)
1521 ; GFX8-NEXT: v_add_f16_e64 v2, v2, 1.0 clamp
1522 ; GFX8-NEXT: flat_store_dword v[0:1], v2
1523 ; GFX8-NEXT: s_endpgm
1524 ;
1525 ; GFX9-LABEL: v_no_clamp_add_src_v2f16_f16_src:
1526 ; GFX9: ; %bb.0:
1527 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1528 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v0
1529 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1530 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1531 ; GFX9-NEXT: global_load_ushort v1, v1, s[2:3]
1532 ; GFX9-NEXT: s_waitcnt vmcnt(0)
1533 ; GFX9-NEXT: v_add_f16_e32 v1, 1.0, v1
1534 ; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 clamp
1535 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
1536 ; GFX9-NEXT: s_endpgm
1537 ;
1538 ; GFX11-LABEL: v_no_clamp_add_src_v2f16_f16_src:
1539 ; GFX11: ; %bb.0:
1540 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1541 ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 1, v0
1542 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1543 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1544 ; GFX11-NEXT: global_load_u16 v1, v1, s[2:3]
1545 ; GFX11-NEXT: s_waitcnt vmcnt(0)
1546 ; GFX11-NEXT: v_add_f16_e32 v1, 1.0, v1
1547 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1548 ; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
1549 ; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 clamp
1550 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1551 ; GFX11-NEXT: s_nop 0
1552 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1553 ; GFX11-NEXT: s_endpgm
1554 %tid = call i32 @llvm.amdgcn.workitem.id.x()
1555 %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid
1556 %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
1557 %a = load half, ptr addrspace(1) %gep0
1558 %add = fadd half %a, 1.0
1559 %bc = bitcast half %add to i16
1560 %zext = zext i16 %bc to i32
1561 %v2f16 = bitcast i32 %zext to <2 x half>
1562 %max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %v2f16, <2 x half> zeroinitializer)
1563 %clamp = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half 1.0>)
1564 store <2 x half> %clamp, ptr addrspace(1) %out.gep
1565 ret void
1566 }
1568 ; FIXME: Worse code pre-gfx9
1570 define <2 x half> @v_clamp_cvt_pkrtz_src_v2f16_denorm(float %a, float %b) #0 {
1571 ; SI-LABEL: v_clamp_cvt_pkrtz_src_v2f16_denorm:
1572 ; SI: ; %bb.0:
1573 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1574 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e32 v0, v0, v1
1575 ; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
1576 ; SI-NEXT: v_cvt_f32_f16_e64 v0, v0 clamp
1577 ; SI-NEXT: v_cvt_f32_f16_e64 v1, v1 clamp
1578 ; SI-NEXT: s_setpc_b64 s[30:31]
1579 ;
1580 ; GFX8-LABEL: v_clamp_cvt_pkrtz_src_v2f16_denorm:
1581 ; GFX8: ; %bb.0:
1582 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1583 ; GFX8-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, v1
1584 ; GFX8-NEXT: v_max_f16_sdwa v1, v0, v0 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
1585 ; GFX8-NEXT: v_max_f16_e64 v0, v0, v0 clamp
1586 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
1587 ; GFX8-NEXT: s_setpc_b64 s[30:31]
1588 ;
1589 ; GFX9-LABEL: v_clamp_cvt_pkrtz_src_v2f16_denorm:
1590 ; GFX9: ; %bb.0:
1591 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1592 ; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, v1 clamp
1593 ; GFX9-NEXT: s_setpc_b64 s[30:31]
1594 ;
1595 ; GFX11-LABEL: v_clamp_cvt_pkrtz_src_v2f16_denorm:
1596 ; GFX11: ; %bb.0:
1597 ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1598 ; GFX11-NEXT: v_cvt_pk_rtz_f16_f32_e64 v0, v0, v1 clamp
1599 ; GFX11-NEXT: s_setpc_b64 s[30:31]
1600 %add = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %a, float %b)
1601 %max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %add, <2 x half> zeroinitializer)
1602 %clamp = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half 1.0>)
1603 ret <2 x half> %clamp
1604 }
1606 declare i32 @llvm.amdgcn.workitem.id.x() #1
1607 declare float @llvm.fabs.f32(float) #1
1608 declare float @llvm.floor.f32(float) #1
1609 declare float @llvm.minnum.f32(float, float) #1
1610 declare float @llvm.maxnum.f32(float, float) #1
1611 declare float @llvm.amdgcn.fmed3.f32(float, float, float) #1
1612 declare double @llvm.fabs.f64(double) #1
1613 declare double @llvm.minnum.f64(double, double) #1
1614 declare double @llvm.maxnum.f64(double, double) #1
1615 declare half @llvm.fabs.f16(half) #1
1616 declare half @llvm.minnum.f16(half, half) #1
1617 declare half @llvm.maxnum.f16(half, half) #1
1618 declare <2 x half> @llvm.minnum.v2f16(<2 x half>, <2 x half>) #1
1619 declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>) #1
1620 declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>) #1
1621 declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>) #1
1622 declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
1625 declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
1627 attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
1628 attributes #1 = { nounwind readnone }
1629 attributes #2 = { nounwind "denormal-fp-math-f32"="ieee.ieee" }
1630 attributes #3 = { nounwind "denormal-fp-math-f32"="ieee,ieee" "denormal-fp-math"="preserve-sign,preserve-sign" }
1632 !llvm.dbg.cu = !{!0}
1633 !llvm.module.flags = !{!2, !3}
1635 !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, isOptimized: true, runtimeVersion: 0, emissionKind: NoDebug)
1636 !1 = !DIFile(filename: "/tmp/foo.cl", directory: "/dev/null")
1637 !2 = !{i32 2, !"Dwarf Version", i32 4}
1638 !3 = !{i32 2, !"Debug Info Version", i32 3}
1639 !4 = !DILocalVariable(name: "add", arg: 1, scope: !5, file: !1, line: 1)
1640 !5 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !6, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0)
1641 !6 = !DISubroutineType(types: !7)
1642 !7 = !{null, !8}
1643 !8 = !DIBasicType(name: "float", size: 32, align: 32)
1644 !9 = !DIExpression()
1645 !10 = !DILocation(line: 1, column: 42, scope: !5)