1 ; RUN: llc -amdgpu-scalarize-global-loads=false -stress-early-ifcvt -amdgpu-early-ifcvt=1 -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
2 ; RUN: llc -amdgpu-scalarize-global-loads=false -stress-early-ifcvt -amdgpu-early-ifcvt=1 -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCNX3 %s
4 ; FIXME: Most of these cases that don't trigger because of broken cost
5 ; heuristics. Should not need -stress-early-ifcvt
7 ; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle64:
8 ; GCN: buffer_load_dwordx2 v[[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]]
9 ; GCN: v_cmp_neq_f64_e32 vcc, 1.0, v[[[VAL_LO]]:[[VAL_HI]]]
10 ; GCN: v_add_f64 v[[[ADD_LO:[0-9]+]]:[[ADD_HI:[0-9]+]]], v[[[VAL_LO]]:[[VAL_HI]]], v[[[VAL_LO]]:[[VAL_HI]]]
11 ; GCN-DAG: v_cndmask_b32_e32 v[[RESULT_LO:[0-9]+]], v[[ADD_LO]], v[[VAL_LO]], vcc
12 ; GCN-DAG: v_cndmask_b32_e32 v[[RESULT_HI:[0-9]+]], v[[ADD_HI]], v[[VAL_HI]], vcc
13 ; GCN: buffer_store_dwordx2 v[[[RESULT_LO]]:[[RESULT_HI]]]
14 define amdgpu_kernel void @test_vccnz_ifcvt_triangle64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
16 %v = load double, ptr addrspace(1) %in
17 %cc = fcmp oeq double %v, 1.000000e+00
18 br i1 %cc, label %if, label %endif
21 %u = fadd double %v, %v
25 %r = phi double [ %v, %entry ], [ %u, %if ]
26 store double %r, ptr addrspace(1) %out
30 ; vcc branch with SGPR inputs
31 ; GCN-LABEL: {{^}}test_vccnz_sgpr_ifcvt_triangle64:
34 ; GCN: v_cndmask_b32_e32
35 ; GCN: v_cndmask_b32_e32
36 define amdgpu_kernel void @test_vccnz_sgpr_ifcvt_triangle64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
38 %v = load double, ptr addrspace(4) %in
39 %cc = fcmp oeq double %v, 1.000000e+00
40 br i1 %cc, label %if, label %endif
43 %u = fadd double %v, %v
47 %r = phi double [ %v, %entry ], [ %u, %if ]
48 store double %r, ptr addrspace(1) %out
52 ; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle96:
53 ; GCN: v_cmp_neq_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 1.0
58 ; GCN: s_mov_b64 vcc, [[CMP]]
60 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
61 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
62 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
64 ; SI-DAG: buffer_store_dwordx2
65 ; SI-DAG: buffer_store_dword v
66 ; GCNX3: buffer_store_dwordx3
67 define amdgpu_kernel void @test_vccnz_ifcvt_triangle96(ptr addrspace(1) %out, ptr addrspace(1) %in, float %cnd) #0 {
69 %v = load <3 x i32>, ptr addrspace(1) %in
70 %cc = fcmp oeq float %cnd, 1.000000e+00
71 br i1 %cc, label %if, label %endif
74 %u = add <3 x i32> %v, %v
78 %r = phi <3 x i32> [ %v, %entry ], [ %u, %if ]
79 store <3 x i32> %r, ptr addrspace(1) %out
83 ; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle128:
84 ; GCN: v_cmp_neq_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 1.0
90 ; GCN: s_mov_b64 vcc, [[CMP]]
92 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
93 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
94 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
95 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
97 ; GCN: buffer_store_dwordx4
98 define amdgpu_kernel void @test_vccnz_ifcvt_triangle128(ptr addrspace(1) %out, ptr addrspace(1) %in, float %cnd) #0 {
100 %v = load <4 x i32>, ptr addrspace(1) %in
101 %cc = fcmp oeq float %cnd, 1.000000e+00
102 br i1 %cc, label %if, label %endif
105 %u = add <4 x i32> %v, %v
109 %r = phi <4 x i32> [ %v, %entry ], [ %u, %if ]
110 store <4 x i32> %r, ptr addrspace(1) %out