| blob | e8423ce9fbc36a292f6c8e0a854f5b4f8dff898e |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX9,GFX9-SDAG
3 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX9,GFX9-GISEL
4 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX10,GFX10-SDAG
5 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX10,GFX10-GISEL
6 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX11,GFX11-SDAG
7 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX11,GFX11-GISEL
9 declare half @llvm.fma.f16(half, half, half)
10 declare half @llvm.maxnum.f16(half, half)
12 define half @test_fma(half %x, half %y, half %z) {
13 ; GFX9-LABEL: test_fma:
14 ; GFX9: ; %bb.0:
15 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
16 ; GFX9-NEXT: v_fma_f16 v0, v0, v1, v2
17 ; GFX9-NEXT: s_setpc_b64 s[30:31]
18 ;
19 ; GFX10-LABEL: test_fma:
20 ; GFX10: ; %bb.0:
21 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
22 ; GFX10-NEXT: v_fma_f16 v0, v0, v1, v2
23 ; GFX10-NEXT: s_setpc_b64 s[30:31]
24 ;
25 ; GFX11-LABEL: test_fma:
26 ; GFX11: ; %bb.0:
27 ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
28 ; GFX11-NEXT: v_fma_f16 v0, v0, v1, v2
29 ; GFX11-NEXT: s_setpc_b64 s[30:31]
30 %r = call half @llvm.fma.f16(half %x, half %y, half %z)
31 ret half %r
32 }
34 ; GFX10+ has v_fmac_f16.
35 define half @test_fmac(half %x, half %y, half %z) {
36 ; GFX9-LABEL: test_fmac:
37 ; GFX9: ; %bb.0:
38 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
39 ; GFX9-NEXT: v_fma_f16 v0, v1, v2, v0
40 ; GFX9-NEXT: s_setpc_b64 s[30:31]
41 ;
42 ; GFX10-LABEL: test_fmac:
43 ; GFX10: ; %bb.0:
44 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
45 ; GFX10-NEXT: v_fmac_f16_e32 v0, v1, v2
46 ; GFX10-NEXT: s_setpc_b64 s[30:31]
47 ;
48 ; GFX11-LABEL: test_fmac:
49 ; GFX11: ; %bb.0:
50 ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
51 ; GFX11-NEXT: v_fmac_f16_e32 v0, v1, v2
52 ; GFX11-NEXT: s_setpc_b64 s[30:31]
53 %r = call half @llvm.fma.f16(half %y, half %z, half %x)
54 ret half %r
55 }
57 ; GFX10+ has v_fmaak_f16.
58 define half @test_fmaak(half %x, half %y, half %z) {
59 ; GFX9-SDAG-LABEL: test_fmaak:
60 ; GFX9-SDAG: ; %bb.0:
61 ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
62 ; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x4200
63 ; GFX9-SDAG-NEXT: v_fma_f16 v0, v0, v1, s4
64 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
65 ;
66 ; GFX9-GISEL-LABEL: test_fmaak:
67 ; GFX9-GISEL: ; %bb.0:
68 ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
69 ; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x4200
70 ; GFX9-GISEL-NEXT: v_fma_f16 v0, v0, v1, v2
71 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
72 ;
73 ; GFX10-LABEL: test_fmaak:
74 ; GFX10: ; %bb.0:
75 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
76 ; GFX10-NEXT: v_fmaak_f16 v0, v0, v1, 0x4200
77 ; GFX10-NEXT: s_setpc_b64 s[30:31]
78 ;
79 ; GFX11-LABEL: test_fmaak:
80 ; GFX11: ; %bb.0:
81 ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
82 ; GFX11-NEXT: v_fmaak_f16 v0, v0, v1, 0x4200
83 ; GFX11-NEXT: s_setpc_b64 s[30:31]
84 %r = call half @llvm.fma.f16(half %x, half %y, half 0xH4200)
85 ret half %r
86 }
88 ; GFX10+ has v_fmamk_f16.
89 define half @test_fmamk(half %x, half %y, half %z) {
90 ; GFX9-SDAG-LABEL: test_fmamk:
91 ; GFX9-SDAG: ; %bb.0:
92 ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
93 ; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x4200
94 ; GFX9-SDAG-NEXT: v_fma_f16 v0, v0, s4, v2
95 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
96 ;
97 ; GFX9-GISEL-LABEL: test_fmamk:
98 ; GFX9-GISEL: ; %bb.0:
99 ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
100 ; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x4200
101 ; GFX9-GISEL-NEXT: v_fma_f16 v0, v0, v1, v2
102 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
103 ;
104 ; GFX10-LABEL: test_fmamk:
105 ; GFX10: ; %bb.0:
106 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
107 ; GFX10-NEXT: v_fmamk_f16 v0, v0, 0x4200, v2
108 ; GFX10-NEXT: s_setpc_b64 s[30:31]
109 ;
110 ; GFX11-LABEL: test_fmamk:
111 ; GFX11: ; %bb.0:
112 ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
113 ; GFX11-NEXT: v_fmamk_f16 v0, v0, 0x4200, v2
114 ; GFX11-NEXT: s_setpc_b64 s[30:31]
115 %r = call half @llvm.fma.f16(half %x, half 0xH4200, half %z)
116 ret half %r
117 }
119 ; Regression test for a crash caused by D139469.
120 define i32 @test_D139469_f16(half %arg) {
121 ; GFX9-SDAG-LABEL: test_D139469_f16:
122 ; GFX9-SDAG: ; %bb.0: ; %bb
123 ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
124 ; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x291e
125 ; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x211e
126 ; GFX9-SDAG-NEXT: v_mul_f16_e32 v1, 0x291e, v0
127 ; GFX9-SDAG-NEXT: v_fma_f16 v0, v0, s4, v2
128 ; GFX9-SDAG-NEXT: v_min_f16_e32 v0, v1, v0
129 ; GFX9-SDAG-NEXT: v_cmp_gt_f16_e32 vcc, 0, v0
130 ; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
131 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
132 ;
133 ; GFX9-GISEL-LABEL: test_D139469_f16:
134 ; GFX9-GISEL: ; %bb.0: ; %bb
135 ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
136 ; GFX9-GISEL-NEXT: v_mul_f16_e32 v1, 0x291e, v0
137 ; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x291e
138 ; GFX9-GISEL-NEXT: v_cmp_gt_f16_e32 vcc, 0, v1
139 ; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x211e
140 ; GFX9-GISEL-NEXT: v_fma_f16 v0, v0, s4, v1
141 ; GFX9-GISEL-NEXT: v_cmp_gt_f16_e64 s[4:5], 0, v0
142 ; GFX9-GISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
143 ; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
144 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
145 ;
146 ; GFX10-SDAG-LABEL: test_D139469_f16:
147 ; GFX10-SDAG: ; %bb.0: ; %bb
148 ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
149 ; GFX10-SDAG-NEXT: v_mov_b32_e32 v1, 0x211e
150 ; GFX10-SDAG-NEXT: v_mul_f16_e32 v2, 0x291e, v0
151 ; GFX10-SDAG-NEXT: v_fmac_f16_e32 v1, 0x291e, v0
152 ; GFX10-SDAG-NEXT: v_min_f16_e32 v0, v2, v1
153 ; GFX10-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0
154 ; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
155 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
156 ;
157 ; GFX10-GISEL-LABEL: test_D139469_f16:
158 ; GFX10-GISEL: ; %bb.0: ; %bb
159 ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
160 ; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x291e
161 ; GFX10-GISEL-NEXT: v_mul_f16_e32 v1, 0x291e, v0
162 ; GFX10-GISEL-NEXT: v_fmaak_f16 v0, s4, v0, 0x211e
163 ; GFX10-GISEL-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1
164 ; GFX10-GISEL-NEXT: v_cmp_gt_f16_e64 s4, 0, v0
165 ; GFX10-GISEL-NEXT: s_or_b32 s4, vcc_lo, s4
166 ; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
167 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
168 ;
169 ; GFX11-SDAG-LABEL: test_D139469_f16:
170 ; GFX11-SDAG: ; %bb.0: ; %bb
171 ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
172 ; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0x211e
173 ; GFX11-SDAG-NEXT: v_mul_f16_e32 v2, 0x291e, v0
174 ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
175 ; GFX11-SDAG-NEXT: v_fmac_f16_e32 v1, 0x291e, v0
176 ; GFX11-SDAG-NEXT: v_min_f16_e32 v0, v2, v1
177 ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
178 ; GFX11-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0
179 ; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
180 ; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
181 ;
182 ; GFX11-GISEL-LABEL: test_D139469_f16:
183 ; GFX11-GISEL: ; %bb.0: ; %bb
184 ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
185 ; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x291e
186 ; GFX11-GISEL-NEXT: v_mul_f16_e32 v1, 0x291e, v0
187 ; GFX11-GISEL-NEXT: v_fmaak_f16 v0, s0, v0, 0x211e
188 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
189 ; GFX11-GISEL-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1
190 ; GFX11-GISEL-NEXT: v_cmp_gt_f16_e64 s0, 0, v0
191 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
192 ; GFX11-GISEL-NEXT: s_or_b32 s0, vcc_lo, s0
193 ; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
194 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
195 bb:
196 %i = fmul contract half %arg, 0xH291E
197 %i1 = fcmp olt half %i, 0xH0000
198 %i2 = fadd contract half %i, 0xH211E
199 %i3 = fcmp olt half %i2, 0xH0000
200 %i4 = or i1 %i1, %i3
201 %i5 = zext i1 %i4 to i32
202 ret i32 %i5
203 }
205 define <2 x i32> @test_D139469_v2f16(<2 x half> %arg) {
206 ; GFX9-SDAG-LABEL: test_D139469_v2f16:
207 ; GFX9-SDAG: ; %bb.0: ; %bb
208 ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
209 ; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x291e
210 ; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x211e
211 ; GFX9-SDAG-NEXT: v_pk_mul_f16 v1, v0, s4 op_sel_hi:[1,0]
212 ; GFX9-SDAG-NEXT: v_pk_fma_f16 v0, v0, s4, v2 op_sel_hi:[1,0,0]
213 ; GFX9-SDAG-NEXT: v_pk_min_f16 v1, v1, v0
214 ; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0
215 ; GFX9-SDAG-NEXT: v_cmp_gt_f16_e32 vcc, 0, v1
216 ; GFX9-SDAG-NEXT: v_cmp_lt_f16_sdwa s[4:5], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
217 ; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
218 ; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
219 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
220 ;
221 ; GFX9-GISEL-LABEL: test_D139469_v2f16:
222 ; GFX9-GISEL: ; %bb.0: ; %bb
223 ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
224 ; GFX9-GISEL-NEXT: s_mov_b32 s4, 0x291e291e
225 ; GFX9-GISEL-NEXT: s_mov_b32 s8, 0
226 ; GFX9-GISEL-NEXT: v_pk_mul_f16 v1, v0, s4
227 ; GFX9-GISEL-NEXT: v_cmp_gt_f16_e32 vcc, 0, v1
228 ; GFX9-GISEL-NEXT: v_cmp_lt_f16_sdwa s[6:7], v1, s8 src0_sel:WORD_1 src1_sel:DWORD
229 ; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x211e211e
230 ; GFX9-GISEL-NEXT: v_pk_fma_f16 v0, v0, s4, v1
231 ; GFX9-GISEL-NEXT: v_cmp_gt_f16_e64 s[4:5], 0, v0
232 ; GFX9-GISEL-NEXT: v_cmp_lt_f16_sdwa s[8:9], v0, s8 src0_sel:WORD_1 src1_sel:DWORD
233 ; GFX9-GISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
234 ; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
235 ; GFX9-GISEL-NEXT: s_or_b64 s[4:5], s[6:7], s[8:9]
236 ; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
237 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
238 ;
239 ; GFX10-SDAG-LABEL: test_D139469_v2f16:
240 ; GFX10-SDAG: ; %bb.0: ; %bb
241 ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
242 ; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x211e
243 ; GFX10-SDAG-NEXT: v_pk_mul_f16 v1, 0x291e, v0 op_sel_hi:[0,1]
244 ; GFX10-SDAG-NEXT: v_pk_fma_f16 v0, 0x291e, v0, s4 op_sel_hi:[0,1,0]
245 ; GFX10-SDAG-NEXT: v_mov_b32_e32 v2, 0
246 ; GFX10-SDAG-NEXT: v_pk_min_f16 v1, v1, v0
247 ; GFX10-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1
248 ; GFX10-SDAG-NEXT: v_cmp_lt_f16_sdwa s4, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
249 ; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
250 ; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
251 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
252 ;
253 ; GFX10-GISEL-LABEL: test_D139469_v2f16:
254 ; GFX10-GISEL: ; %bb.0: ; %bb
255 ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
256 ; GFX10-GISEL-NEXT: s_mov_b32 s4, 0x291e291e
257 ; GFX10-GISEL-NEXT: v_pk_mul_f16 v1, v0, 0x291e op_sel_hi:[1,0]
258 ; GFX10-GISEL-NEXT: v_pk_fma_f16 v0, v0, s4, 0x211e op_sel_hi:[1,1,0]
259 ; GFX10-GISEL-NEXT: s_mov_b32 s5, 0
260 ; GFX10-GISEL-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1
261 ; GFX10-GISEL-NEXT: v_cmp_gt_f16_e64 s4, 0, v0
262 ; GFX10-GISEL-NEXT: v_cmp_lt_f16_sdwa s6, v1, s5 src0_sel:WORD_1 src1_sel:DWORD
263 ; GFX10-GISEL-NEXT: v_cmp_lt_f16_sdwa s5, v0, s5 src0_sel:WORD_1 src1_sel:DWORD
264 ; GFX10-GISEL-NEXT: s_or_b32 s4, vcc_lo, s4
265 ; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
266 ; GFX10-GISEL-NEXT: s_or_b32 s4, s6, s5
267 ; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
268 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
269 ;
270 ; GFX11-SDAG-LABEL: test_D139469_v2f16:
271 ; GFX11-SDAG: ; %bb.0: ; %bb
272 ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
273 ; GFX11-SDAG-NEXT: s_movk_i32 s0, 0x211e
274 ; GFX11-SDAG-NEXT: v_pk_mul_f16 v1, 0x291e, v0 op_sel_hi:[0,1]
275 ; GFX11-SDAG-NEXT: v_pk_fma_f16 v0, 0x291e, v0, s0 op_sel_hi:[0,1,0]
276 ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
277 ; GFX11-SDAG-NEXT: v_pk_min_f16 v0, v1, v0
278 ; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
279 ; GFX11-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0
280 ; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
281 ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
282 ; GFX11-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1
283 ; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
284 ; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
285 ;
286 ; GFX11-GISEL-LABEL: test_D139469_v2f16:
287 ; GFX11-GISEL: ; %bb.0: ; %bb
288 ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
289 ; GFX11-GISEL-NEXT: s_mov_b32 s0, 0x291e291e
290 ; GFX11-GISEL-NEXT: v_pk_mul_f16 v1, v0, 0x291e op_sel_hi:[1,0]
291 ; GFX11-GISEL-NEXT: v_pk_fma_f16 v0, v0, s0, 0x211e op_sel_hi:[1,1,0]
292 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
293 ; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v1
294 ; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v0
295 ; GFX11-GISEL-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1
296 ; GFX11-GISEL-NEXT: v_cmp_gt_f16_e64 s0, 0, v0
297 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
298 ; GFX11-GISEL-NEXT: v_cmp_gt_f16_e64 s1, 0, v2
299 ; GFX11-GISEL-NEXT: v_cmp_gt_f16_e64 s2, 0, v3
300 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
301 ; GFX11-GISEL-NEXT: s_or_b32 s0, vcc_lo, s0
302 ; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
303 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
304 ; GFX11-GISEL-NEXT: s_or_b32 s0, s1, s2
305 ; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
306 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
307 bb:
308 %i = fmul contract <2 x half> %arg, <half 0xH291E, half 0xH291E>
309 %i1 = fcmp olt <2 x half> %i, <half 0xH0000, half 0xH0000>
310 %i2 = fadd contract <2 x half> %i, <half 0xH211E, half 0xH211E>
311 %i3 = fcmp olt <2 x half> %i2, <half 0xH0000, half 0xH0000>
312 %i4 = or <2 x i1> %i1, %i3
313 %i5 = zext <2 x i1> %i4 to <2 x i32>
314 ret <2 x i32> %i5
315 }