| blob | 20dc5b7d77c2af27a09a8c84af0921664df8d66d |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=SICI,SI %s
3 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=SICI,CI %s
4 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=VI %s
5 ; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
7 declare half @llvm.nearbyint.f16(half) #0
8 declare float @llvm.nearbyint.f32(float) #0
9 declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) #0
10 declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) #0
11 declare double @llvm.nearbyint.f64(double) #0
12 declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) #0
13 declare <4 x double> @llvm.nearbyint.v4f64(<4 x double>) #0
15 define amdgpu_kernel void @fnearbyint_f16(ptr addrspace(1) %out, half %in) #1 {
16 ; SI-LABEL: fnearbyint_f16:
17 ; SI: ; %bb.0:
18 ; SI-NEXT: s_load_dword s4, s[0:1], 0xb
19 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
20 ; SI-NEXT: s_mov_b32 s3, 0xf000
21 ; SI-NEXT: s_mov_b32 s2, -1
22 ; SI-NEXT: s_waitcnt lgkmcnt(0)
23 ; SI-NEXT: v_cvt_f32_f16_e32 v0, s4
24 ; SI-NEXT: v_rndne_f32_e32 v0, v0
25 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
26 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
27 ; SI-NEXT: s_endpgm
28 ;
29 ; CI-LABEL: fnearbyint_f16:
30 ; CI: ; %bb.0:
31 ; CI-NEXT: s_load_dword s2, s[0:1], 0xb
32 ; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
33 ; CI-NEXT: s_mov_b32 s3, 0xf000
34 ; CI-NEXT: s_waitcnt lgkmcnt(0)
35 ; CI-NEXT: v_cvt_f32_f16_e32 v0, s2
36 ; CI-NEXT: s_mov_b32 s2, -1
37 ; CI-NEXT: v_rndne_f32_e32 v0, v0
38 ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
39 ; CI-NEXT: buffer_store_short v0, off, s[0:3], 0
40 ; CI-NEXT: s_endpgm
41 ;
42 ; VI-LABEL: fnearbyint_f16:
43 ; VI: ; %bb.0:
44 ; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
45 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
46 ; VI-NEXT: s_waitcnt lgkmcnt(0)
47 ; VI-NEXT: v_rndne_f16_e32 v2, s2
48 ; VI-NEXT: v_mov_b32_e32 v0, s0
49 ; VI-NEXT: v_mov_b32_e32 v1, s1
50 ; VI-NEXT: flat_store_short v[0:1], v2
51 ; VI-NEXT: s_endpgm
52 ;
53 ; GFX11-LABEL: fnearbyint_f16:
54 ; GFX11: ; %bb.0:
55 ; GFX11-NEXT: s_clause 0x1
56 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
57 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
58 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
59 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
60 ; GFX11-NEXT: v_rndne_f16_e32 v1, s2
61 ; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
62 ; GFX11-NEXT: s_nop 0
63 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
64 ; GFX11-NEXT: s_endpgm
65 %1 = call half @llvm.nearbyint.f16(half %in)
66 store half %1, ptr addrspace(1) %out
67 ret void
68 }
70 define amdgpu_kernel void @fnearbyint_f32(ptr addrspace(1) %out, float %in) #1 {
71 ; SICI-LABEL: fnearbyint_f32:
72 ; SICI: ; %bb.0: ; %entry
73 ; SICI-NEXT: s_load_dword s4, s[0:1], 0xb
74 ; SICI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
75 ; SICI-NEXT: s_mov_b32 s3, 0xf000
76 ; SICI-NEXT: s_mov_b32 s2, -1
77 ; SICI-NEXT: s_waitcnt lgkmcnt(0)
78 ; SICI-NEXT: v_rndne_f32_e32 v0, s4
79 ; SICI-NEXT: buffer_store_dword v0, off, s[0:3], 0
80 ; SICI-NEXT: s_endpgm
81 ;
82 ; VI-LABEL: fnearbyint_f32:
83 ; VI: ; %bb.0: ; %entry
84 ; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
85 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
86 ; VI-NEXT: s_waitcnt lgkmcnt(0)
87 ; VI-NEXT: v_rndne_f32_e32 v2, s2
88 ; VI-NEXT: v_mov_b32_e32 v0, s0
89 ; VI-NEXT: v_mov_b32_e32 v1, s1
90 ; VI-NEXT: flat_store_dword v[0:1], v2
91 ; VI-NEXT: s_endpgm
92 ;
93 ; GFX11-LABEL: fnearbyint_f32:
94 ; GFX11: ; %bb.0: ; %entry
95 ; GFX11-NEXT: s_clause 0x1
96 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
97 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
98 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
99 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
100 ; GFX11-NEXT: v_rndne_f32_e32 v1, s2
101 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
102 ; GFX11-NEXT: s_nop 0
103 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
104 ; GFX11-NEXT: s_endpgm
105 entry:
106 %0 = call float @llvm.nearbyint.f32(float %in)
107 store float %0, ptr addrspace(1) %out
108 ret void
109 }
111 define amdgpu_kernel void @fnearbyint_v2f32(ptr addrspace(1) %out, <2 x float> %in) #1 {
112 ; SICI-LABEL: fnearbyint_v2f32:
113 ; SICI: ; %bb.0: ; %entry
114 ; SICI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
115 ; SICI-NEXT: s_mov_b32 s7, 0xf000
116 ; SICI-NEXT: s_mov_b32 s6, -1
117 ; SICI-NEXT: s_waitcnt lgkmcnt(0)
118 ; SICI-NEXT: s_mov_b32 s4, s0
119 ; SICI-NEXT: s_mov_b32 s5, s1
120 ; SICI-NEXT: v_rndne_f32_e32 v1, s3
121 ; SICI-NEXT: v_rndne_f32_e32 v0, s2
122 ; SICI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
123 ; SICI-NEXT: s_endpgm
124 ;
125 ; VI-LABEL: fnearbyint_v2f32:
126 ; VI: ; %bb.0: ; %entry
127 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
128 ; VI-NEXT: s_waitcnt lgkmcnt(0)
129 ; VI-NEXT: v_mov_b32_e32 v3, s1
130 ; VI-NEXT: v_rndne_f32_e32 v1, s3
131 ; VI-NEXT: v_rndne_f32_e32 v0, s2
132 ; VI-NEXT: v_mov_b32_e32 v2, s0
133 ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
134 ; VI-NEXT: s_endpgm
135 ;
136 ; GFX11-LABEL: fnearbyint_v2f32:
137 ; GFX11: ; %bb.0: ; %entry
138 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
139 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
140 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
141 ; GFX11-NEXT: v_rndne_f32_e32 v1, s3
142 ; GFX11-NEXT: v_rndne_f32_e32 v0, s2
143 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
144 ; GFX11-NEXT: s_nop 0
145 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
146 ; GFX11-NEXT: s_endpgm
147 entry:
148 %0 = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %in)
149 store <2 x float> %0, ptr addrspace(1) %out
150 ret void
151 }
153 define amdgpu_kernel void @fnearbyint_v4f32(ptr addrspace(1) %out, <4 x float> %in) #1 {
154 ; SICI-LABEL: fnearbyint_v4f32:
155 ; SICI: ; %bb.0: ; %entry
156 ; SICI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd
157 ; SICI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
158 ; SICI-NEXT: s_mov_b32 s3, 0xf000
159 ; SICI-NEXT: s_mov_b32 s2, -1
160 ; SICI-NEXT: s_waitcnt lgkmcnt(0)
161 ; SICI-NEXT: v_rndne_f32_e32 v3, s7
162 ; SICI-NEXT: v_rndne_f32_e32 v2, s6
163 ; SICI-NEXT: v_rndne_f32_e32 v1, s5
164 ; SICI-NEXT: v_rndne_f32_e32 v0, s4
165 ; SICI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
166 ; SICI-NEXT: s_endpgm
167 ;
168 ; VI-LABEL: fnearbyint_v4f32:
169 ; VI: ; %bb.0: ; %entry
170 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
171 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
172 ; VI-NEXT: s_waitcnt lgkmcnt(0)
173 ; VI-NEXT: v_rndne_f32_e32 v3, s7
174 ; VI-NEXT: v_mov_b32_e32 v5, s1
175 ; VI-NEXT: v_rndne_f32_e32 v2, s6
176 ; VI-NEXT: v_rndne_f32_e32 v1, s5
177 ; VI-NEXT: v_rndne_f32_e32 v0, s4
178 ; VI-NEXT: v_mov_b32_e32 v4, s0
179 ; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
180 ; VI-NEXT: s_endpgm
181 ;
182 ; GFX11-LABEL: fnearbyint_v4f32:
183 ; GFX11: ; %bb.0: ; %entry
184 ; GFX11-NEXT: s_clause 0x1
185 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x34
186 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
187 ; GFX11-NEXT: v_mov_b32_e32 v4, 0
188 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
189 ; GFX11-NEXT: v_rndne_f32_e32 v3, s7
190 ; GFX11-NEXT: v_rndne_f32_e32 v2, s6
191 ; GFX11-NEXT: v_rndne_f32_e32 v1, s5
192 ; GFX11-NEXT: v_rndne_f32_e32 v0, s4
193 ; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]
194 ; GFX11-NEXT: s_nop 0
195 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
196 ; GFX11-NEXT: s_endpgm
197 entry:
198 %0 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %in)
199 store <4 x float> %0, ptr addrspace(1) %out
200 ret void
201 }
203 define amdgpu_kernel void @nearbyint_f64(ptr addrspace(1) %out, double %in) {
204 ; SI-LABEL: nearbyint_f64:
205 ; SI: ; %bb.0: ; %entry
206 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
207 ; SI-NEXT: s_mov_b32 s7, 0xf000
208 ; SI-NEXT: s_mov_b32 s6, -1
209 ; SI-NEXT: s_brev_b32 s8, -2
210 ; SI-NEXT: v_mov_b32_e32 v1, 0x43300000
211 ; SI-NEXT: v_mov_b32_e32 v0, 0
212 ; SI-NEXT: v_mov_b32_e32 v2, -1
213 ; SI-NEXT: v_mov_b32_e32 v3, 0x432fffff
214 ; SI-NEXT: s_waitcnt lgkmcnt(0)
215 ; SI-NEXT: s_mov_b32 s4, s0
216 ; SI-NEXT: s_mov_b32 s5, s1
217 ; SI-NEXT: v_mov_b32_e32 v6, s3
218 ; SI-NEXT: v_bfi_b32 v1, s8, v1, v6
219 ; SI-NEXT: v_mov_b32_e32 v7, s2
220 ; SI-NEXT: v_add_f64 v[4:5], s[2:3], v[0:1]
221 ; SI-NEXT: v_add_f64 v[0:1], v[4:5], -v[0:1]
222 ; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[2:3]|, v[2:3]
223 ; SI-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
224 ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
225 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
226 ; SI-NEXT: s_endpgm
227 ;
228 ; CI-LABEL: nearbyint_f64:
229 ; CI: ; %bb.0: ; %entry
230 ; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
231 ; CI-NEXT: s_waitcnt lgkmcnt(0)
232 ; CI-NEXT: v_rndne_f64_e32 v[0:1], s[2:3]
233 ; CI-NEXT: s_mov_b32 s3, 0xf000
234 ; CI-NEXT: s_mov_b32 s2, -1
235 ; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
236 ; CI-NEXT: s_endpgm
237 ;
238 ; VI-LABEL: nearbyint_f64:
239 ; VI: ; %bb.0: ; %entry
240 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
241 ; VI-NEXT: s_waitcnt lgkmcnt(0)
242 ; VI-NEXT: v_rndne_f64_e32 v[0:1], s[2:3]
243 ; VI-NEXT: v_mov_b32_e32 v2, s0
244 ; VI-NEXT: v_mov_b32_e32 v3, s1
245 ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
246 ; VI-NEXT: s_endpgm
247 ;
248 ; GFX11-LABEL: nearbyint_f64:
249 ; GFX11: ; %bb.0: ; %entry
250 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
251 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
252 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
253 ; GFX11-NEXT: v_rndne_f64_e32 v[0:1], s[2:3]
254 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
255 ; GFX11-NEXT: s_nop 0
256 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
257 ; GFX11-NEXT: s_endpgm
258 entry:
259 %0 = call double @llvm.nearbyint.f64(double %in)
260 store double %0, ptr addrspace(1) %out
261 ret void
262 }
263 define amdgpu_kernel void @nearbyint_v2f64(ptr addrspace(1) %out, <2 x double> %in) {
264 ; SI-LABEL: nearbyint_v2f64:
265 ; SI: ; %bb.0: ; %entry
266 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
267 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
268 ; SI-NEXT: s_mov_b32 s7, 0xf000
269 ; SI-NEXT: s_mov_b32 s6, -1
270 ; SI-NEXT: s_brev_b32 s10, -2
271 ; SI-NEXT: v_mov_b32_e32 v6, 0x43300000
272 ; SI-NEXT: s_mov_b32 s9, 0x432fffff
273 ; SI-NEXT: v_mov_b32_e32 v0, 0
274 ; SI-NEXT: s_mov_b32 s8, s6
275 ; SI-NEXT: v_mov_b32_e32 v4, s8
276 ; SI-NEXT: v_mov_b32_e32 v5, s9
277 ; SI-NEXT: s_waitcnt lgkmcnt(0)
278 ; SI-NEXT: v_mov_b32_e32 v7, s3
279 ; SI-NEXT: v_bfi_b32 v1, s10, v6, v7
280 ; SI-NEXT: v_mov_b32_e32 v8, s2
281 ; SI-NEXT: v_mov_b32_e32 v9, s1
282 ; SI-NEXT: v_mov_b32_e32 v10, s0
283 ; SI-NEXT: v_add_f64 v[2:3], s[2:3], v[0:1]
284 ; SI-NEXT: v_add_f64 v[2:3], v[2:3], -v[0:1]
285 ; SI-NEXT: v_bfi_b32 v1, s10, v6, v9
286 ; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[2:3]|, v[4:5]
287 ; SI-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
288 ; SI-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
289 ; SI-NEXT: v_add_f64 v[6:7], s[0:1], v[0:1]
290 ; SI-NEXT: v_add_f64 v[0:1], v[6:7], -v[0:1]
291 ; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[0:1]|, v[4:5]
292 ; SI-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
293 ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
294 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
295 ; SI-NEXT: s_endpgm
296 ;
297 ; CI-LABEL: nearbyint_v2f64:
298 ; CI: ; %bb.0: ; %entry
299 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd
300 ; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
301 ; CI-NEXT: s_mov_b32 s3, 0xf000
302 ; CI-NEXT: s_mov_b32 s2, -1
303 ; CI-NEXT: s_waitcnt lgkmcnt(0)
304 ; CI-NEXT: v_rndne_f64_e32 v[2:3], s[6:7]
305 ; CI-NEXT: v_rndne_f64_e32 v[0:1], s[4:5]
306 ; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
307 ; CI-NEXT: s_endpgm
308 ;
309 ; VI-LABEL: nearbyint_v2f64:
310 ; VI: ; %bb.0: ; %entry
311 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
312 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
313 ; VI-NEXT: s_waitcnt lgkmcnt(0)
314 ; VI-NEXT: v_rndne_f64_e32 v[2:3], s[6:7]
315 ; VI-NEXT: v_rndne_f64_e32 v[0:1], s[4:5]
316 ; VI-NEXT: v_mov_b32_e32 v5, s1
317 ; VI-NEXT: v_mov_b32_e32 v4, s0
318 ; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
319 ; VI-NEXT: s_endpgm
320 ;
321 ; GFX11-LABEL: nearbyint_v2f64:
322 ; GFX11: ; %bb.0: ; %entry
323 ; GFX11-NEXT: s_clause 0x1
324 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x34
325 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
326 ; GFX11-NEXT: v_mov_b32_e32 v4, 0
327 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
328 ; GFX11-NEXT: v_rndne_f64_e32 v[2:3], s[6:7]
329 ; GFX11-NEXT: v_rndne_f64_e32 v[0:1], s[4:5]
330 ; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]
331 ; GFX11-NEXT: s_nop 0
332 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
333 ; GFX11-NEXT: s_endpgm
334 entry:
335 %0 = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %in)
336 store <2 x double> %0, ptr addrspace(1) %out
337 ret void
338 }
340 define amdgpu_kernel void @nearbyint_v4f64(ptr addrspace(1) %out, <4 x double> %in) {
341 ; SI-LABEL: nearbyint_v4f64:
342 ; SI: ; %bb.0: ; %entry
343 ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
344 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x11
345 ; SI-NEXT: s_mov_b32 s11, 0xf000
346 ; SI-NEXT: s_mov_b32 s10, -1
347 ; SI-NEXT: s_brev_b32 s14, -2
348 ; SI-NEXT: v_mov_b32_e32 v10, 0x43300000
349 ; SI-NEXT: s_mov_b32 s13, 0x432fffff
350 ; SI-NEXT: v_mov_b32_e32 v4, 0
351 ; SI-NEXT: s_mov_b32 s12, s10
352 ; SI-NEXT: v_mov_b32_e32 v8, s12
353 ; SI-NEXT: v_mov_b32_e32 v9, s13
354 ; SI-NEXT: s_waitcnt lgkmcnt(0)
355 ; SI-NEXT: v_mov_b32_e32 v2, s3
356 ; SI-NEXT: v_bfi_b32 v5, s14, v10, v2
357 ; SI-NEXT: v_mov_b32_e32 v6, s2
358 ; SI-NEXT: v_mov_b32_e32 v7, s1
359 ; SI-NEXT: v_mov_b32_e32 v11, s0
360 ; SI-NEXT: v_mov_b32_e32 v12, s7
361 ; SI-NEXT: v_mov_b32_e32 v13, s6
362 ; SI-NEXT: v_mov_b32_e32 v14, s5
363 ; SI-NEXT: v_mov_b32_e32 v15, s4
364 ; SI-NEXT: v_add_f64 v[0:1], s[2:3], v[4:5]
365 ; SI-NEXT: v_add_f64 v[0:1], v[0:1], -v[4:5]
366 ; SI-NEXT: v_bfi_b32 v5, s14, v10, v7
367 ; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[2:3]|, v[8:9]
368 ; SI-NEXT: v_cndmask_b32_e32 v3, v1, v2, vcc
369 ; SI-NEXT: v_cndmask_b32_e32 v2, v0, v6, vcc
370 ; SI-NEXT: v_add_f64 v[0:1], s[0:1], v[4:5]
371 ; SI-NEXT: v_add_f64 v[0:1], v[0:1], -v[4:5]
372 ; SI-NEXT: v_bfi_b32 v5, s14, v10, v12
373 ; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[0:1]|, v[8:9]
374 ; SI-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
375 ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v11, vcc
376 ; SI-NEXT: v_add_f64 v[6:7], s[6:7], v[4:5]
377 ; SI-NEXT: v_add_f64 v[6:7], v[6:7], -v[4:5]
378 ; SI-NEXT: v_bfi_b32 v5, s14, v10, v14
379 ; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[6:7]|, v[8:9]
380 ; SI-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc
381 ; SI-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc
382 ; SI-NEXT: v_add_f64 v[10:11], s[4:5], v[4:5]
383 ; SI-NEXT: v_add_f64 v[4:5], v[10:11], -v[4:5]
384 ; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[4:5]|, v[8:9]
385 ; SI-NEXT: v_cndmask_b32_e32 v5, v5, v14, vcc
386 ; SI-NEXT: v_cndmask_b32_e32 v4, v4, v15, vcc
387 ; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
388 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
389 ; SI-NEXT: s_endpgm
390 ;
391 ; CI-LABEL: nearbyint_v4f64:
392 ; CI: ; %bb.0: ; %entry
393 ; CI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x11
394 ; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
395 ; CI-NEXT: s_mov_b32 s3, 0xf000
396 ; CI-NEXT: s_mov_b32 s2, -1
397 ; CI-NEXT: s_waitcnt lgkmcnt(0)
398 ; CI-NEXT: v_rndne_f64_e32 v[6:7], s[10:11]
399 ; CI-NEXT: v_rndne_f64_e32 v[4:5], s[8:9]
400 ; CI-NEXT: v_rndne_f64_e32 v[2:3], s[6:7]
401 ; CI-NEXT: v_rndne_f64_e32 v[0:1], s[4:5]
402 ; CI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
403 ; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
404 ; CI-NEXT: s_endpgm
405 ;
406 ; VI-LABEL: nearbyint_v4f64:
407 ; VI: ; %bb.0: ; %entry
408 ; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x44
409 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
410 ; VI-NEXT: s_waitcnt lgkmcnt(0)
411 ; VI-NEXT: v_rndne_f64_e32 v[6:7], s[10:11]
412 ; VI-NEXT: v_rndne_f64_e32 v[4:5], s[8:9]
413 ; VI-NEXT: v_rndne_f64_e32 v[2:3], s[6:7]
414 ; VI-NEXT: v_rndne_f64_e32 v[0:1], s[4:5]
415 ; VI-NEXT: s_add_u32 s2, s0, 16
416 ; VI-NEXT: s_addc_u32 s3, s1, 0
417 ; VI-NEXT: v_mov_b32_e32 v11, s3
418 ; VI-NEXT: v_mov_b32_e32 v9, s1
419 ; VI-NEXT: v_mov_b32_e32 v10, s2
420 ; VI-NEXT: v_mov_b32_e32 v8, s0
421 ; VI-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
422 ; VI-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
423 ; VI-NEXT: s_endpgm
424 ;
425 ; GFX11-LABEL: nearbyint_v4f64:
426 ; GFX11: ; %bb.0: ; %entry
427 ; GFX11-NEXT: s_clause 0x1
428 ; GFX11-NEXT: s_load_b256 s[4:11], s[0:1], 0x44
429 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
430 ; GFX11-NEXT: v_mov_b32_e32 v8, 0
431 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
432 ; GFX11-NEXT: v_rndne_f64_e32 v[6:7], s[10:11]
433 ; GFX11-NEXT: v_rndne_f64_e32 v[4:5], s[8:9]
434 ; GFX11-NEXT: v_rndne_f64_e32 v[2:3], s[6:7]
435 ; GFX11-NEXT: v_rndne_f64_e32 v[0:1], s[4:5]
436 ; GFX11-NEXT: s_clause 0x1
437 ; GFX11-NEXT: global_store_b128 v8, v[4:7], s[0:1] offset:16
438 ; GFX11-NEXT: global_store_b128 v8, v[0:3], s[0:1]
439 ; GFX11-NEXT: s_nop 0
440 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
441 ; GFX11-NEXT: s_endpgm
442 entry:
443 %0 = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %in)
444 store <4 x double> %0, ptr addrspace(1) %out
445 ret void
446 }
448 attributes #0 = { nounwind readonly }
449 attributes #1 = { nounwind }