| blob | 31c1389c9402080056fb371e8428675c5c4d6bb5 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2 ; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=kaveri -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CIVI,CI %s
3 ; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=tonga -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CIVI,GFX8 %s
4 ; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx900 -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s
5 ; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx1100 -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
7 ; FIXME: Should be able to do scalar op
8 define amdgpu_kernel void @s_fneg_f16(ptr addrspace(1) %out, half %in) #0 {
9 ; CI-LABEL: s_fneg_f16:
10 ; CI: ; %bb.0:
11 ; CI-NEXT: s_load_dword s2, s[4:5], 0x2
12 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
13 ; CI-NEXT: s_waitcnt lgkmcnt(0)
14 ; CI-NEXT: s_xor_b32 s2, s2, 0x8000
15 ; CI-NEXT: v_mov_b32_e32 v0, s0
16 ; CI-NEXT: v_mov_b32_e32 v1, s1
17 ; CI-NEXT: v_mov_b32_e32 v2, s2
18 ; CI-NEXT: flat_store_short v[0:1], v2
19 ; CI-NEXT: s_endpgm
20 ;
21 ; GFX8-LABEL: s_fneg_f16:
22 ; GFX8: ; %bb.0:
23 ; GFX8-NEXT: s_load_dword s2, s[4:5], 0x8
24 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
25 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
26 ; GFX8-NEXT: s_xor_b32 s2, s2, 0x8000
27 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
28 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
29 ; GFX8-NEXT: v_mov_b32_e32 v2, s2
30 ; GFX8-NEXT: flat_store_short v[0:1], v2
31 ; GFX8-NEXT: s_endpgm
32 ;
33 ; GFX9-LABEL: s_fneg_f16:
34 ; GFX9: ; %bb.0:
35 ; GFX9-NEXT: s_load_dword s2, s[4:5], 0x8
36 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
37 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
38 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
39 ; GFX9-NEXT: s_xor_b32 s2, s2, 0x8000
40 ; GFX9-NEXT: v_mov_b32_e32 v1, s2
41 ; GFX9-NEXT: global_store_short v0, v1, s[0:1]
42 ; GFX9-NEXT: s_endpgm
43 ;
44 ; GFX11-LABEL: s_fneg_f16:
45 ; GFX11: ; %bb.0:
46 ; GFX11-NEXT: s_clause 0x1
47 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x8
48 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
49 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
50 ; GFX11-NEXT: s_xor_b32 s2, s2, 0x8000
51 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
52 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
53 ; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
54 ; GFX11-NEXT: s_nop 0
55 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
56 ; GFX11-NEXT: s_endpgm
57 %fneg = fsub half -0.0, %in
58 store half %fneg, ptr addrspace(1) %out
59 ret void
60 }
62 ; FIXME: Should be able to use bit operations when illegal type as
63 ; well.
64 define amdgpu_kernel void @v_fneg_f16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
65 ; CI-LABEL: v_fneg_f16:
66 ; CI: ; %bb.0:
67 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2
68 ; CI-NEXT: v_lshlrev_b32_e32 v0, 1, v0
69 ; CI-NEXT: s_waitcnt lgkmcnt(0)
70 ; CI-NEXT: v_mov_b32_e32 v1, s1
71 ; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0
72 ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
73 ; CI-NEXT: flat_load_ushort v2, v[0:1]
74 ; CI-NEXT: s_waitcnt vmcnt(0)
75 ; CI-NEXT: v_xor_b32_e32 v2, 0x8000, v2
76 ; CI-NEXT: flat_store_short v[0:1], v2
77 ; CI-NEXT: s_endpgm
78 ;
79 ; GFX8-LABEL: v_fneg_f16:
80 ; GFX8: ; %bb.0:
81 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
82 ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
83 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
84 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
85 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
86 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
87 ; GFX8-NEXT: flat_load_ushort v2, v[0:1]
88 ; GFX8-NEXT: s_waitcnt vmcnt(0)
89 ; GFX8-NEXT: v_xor_b32_e32 v2, 0x8000, v2
90 ; GFX8-NEXT: flat_store_short v[0:1], v2
91 ; GFX8-NEXT: s_endpgm
92 ;
93 ; GFX9-LABEL: v_fneg_f16:
94 ; GFX9: ; %bb.0:
95 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
96 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
97 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
98 ; GFX9-NEXT: global_load_ushort v1, v0, s[0:1]
99 ; GFX9-NEXT: s_waitcnt vmcnt(0)
100 ; GFX9-NEXT: v_xor_b32_e32 v1, 0x8000, v1
101 ; GFX9-NEXT: global_store_short v0, v1, s[0:1]
102 ; GFX9-NEXT: s_endpgm
103 ;
104 ; GFX11-LABEL: v_fneg_f16:
105 ; GFX11: ; %bb.0:
106 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x8
107 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0
108 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
109 ; GFX11-NEXT: global_load_u16 v1, v0, s[0:1]
110 ; GFX11-NEXT: s_waitcnt vmcnt(0)
111 ; GFX11-NEXT: v_xor_b32_e32 v1, 0x8000, v1
112 ; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
113 ; GFX11-NEXT: s_nop 0
114 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
115 ; GFX11-NEXT: s_endpgm
116 %tid = call i32 @llvm.amdgcn.workitem.id.x()
117 %gep.in = getelementptr inbounds half, ptr addrspace(1) %in, i32 %tid
118 %gep.out = getelementptr inbounds half, ptr addrspace(1) %in, i32 %tid
119 %val = load half, ptr addrspace(1) %gep.in, align 2
120 %fneg = fsub half -0.0, %val
121 store half %fneg, ptr addrspace(1) %gep.out
122 ret void
123 }
125 define amdgpu_kernel void @s_fneg_free_f16(ptr addrspace(1) %out, i16 %in) #0 {
126 ; CI-LABEL: s_fneg_free_f16:
127 ; CI: ; %bb.0:
128 ; CI-NEXT: s_load_dword s2, s[4:5], 0x2
129 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
130 ; CI-NEXT: s_waitcnt lgkmcnt(0)
131 ; CI-NEXT: s_xor_b32 s2, s2, 0x8000
132 ; CI-NEXT: v_mov_b32_e32 v0, s0
133 ; CI-NEXT: v_mov_b32_e32 v1, s1
134 ; CI-NEXT: v_mov_b32_e32 v2, s2
135 ; CI-NEXT: flat_store_short v[0:1], v2
136 ; CI-NEXT: s_endpgm
137 ;
138 ; GFX8-LABEL: s_fneg_free_f16:
139 ; GFX8: ; %bb.0:
140 ; GFX8-NEXT: s_load_dword s2, s[4:5], 0x8
141 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
142 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
143 ; GFX8-NEXT: s_xor_b32 s2, s2, 0x8000
144 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
145 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
146 ; GFX8-NEXT: v_mov_b32_e32 v2, s2
147 ; GFX8-NEXT: flat_store_short v[0:1], v2
148 ; GFX8-NEXT: s_endpgm
149 ;
150 ; GFX9-LABEL: s_fneg_free_f16:
151 ; GFX9: ; %bb.0:
152 ; GFX9-NEXT: s_load_dword s2, s[4:5], 0x8
153 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
154 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
155 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
156 ; GFX9-NEXT: s_xor_b32 s2, s2, 0x8000
157 ; GFX9-NEXT: v_mov_b32_e32 v1, s2
158 ; GFX9-NEXT: global_store_short v0, v1, s[0:1]
159 ; GFX9-NEXT: s_endpgm
160 ;
161 ; GFX11-LABEL: s_fneg_free_f16:
162 ; GFX11: ; %bb.0:
163 ; GFX11-NEXT: s_clause 0x1
164 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x8
165 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
166 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
167 ; GFX11-NEXT: s_xor_b32 s2, s2, 0x8000
168 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
169 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
170 ; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
171 ; GFX11-NEXT: s_nop 0
172 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
173 ; GFX11-NEXT: s_endpgm
174 %bc = bitcast i16 %in to half
175 %fsub = fsub half -0.0, %bc
176 store half %fsub, ptr addrspace(1) %out
177 ret void
178 }
180 define amdgpu_kernel void @v_fneg_fold_f16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
181 ; CI-LABEL: v_fneg_fold_f16:
182 ; CI: ; %bb.0:
183 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
184 ; CI-NEXT: s_waitcnt lgkmcnt(0)
185 ; CI-NEXT: v_mov_b32_e32 v0, s2
186 ; CI-NEXT: v_mov_b32_e32 v1, s3
187 ; CI-NEXT: flat_load_ushort v0, v[0:1]
188 ; CI-NEXT: s_waitcnt vmcnt(0)
189 ; CI-NEXT: v_cvt_f32_f16_e32 v1, v0
190 ; CI-NEXT: v_cvt_f32_f16_e64 v0, -v0
191 ; CI-NEXT: v_mul_f32_e32 v0, v0, v1
192 ; CI-NEXT: v_cvt_f16_f32_e32 v2, v0
193 ; CI-NEXT: v_mov_b32_e32 v0, s0
194 ; CI-NEXT: v_mov_b32_e32 v1, s1
195 ; CI-NEXT: flat_store_short v[0:1], v2
196 ; CI-NEXT: s_endpgm
197 ;
198 ; GFX8-LABEL: v_fneg_fold_f16:
199 ; GFX8: ; %bb.0:
200 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
201 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
202 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
203 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
204 ; GFX8-NEXT: flat_load_ushort v2, v[0:1]
205 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
206 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
207 ; GFX8-NEXT: s_waitcnt vmcnt(0)
208 ; GFX8-NEXT: v_mul_f16_e64 v2, -v2, v2
209 ; GFX8-NEXT: flat_store_short v[0:1], v2
210 ; GFX8-NEXT: s_endpgm
211 ;
212 ; GFX9-LABEL: v_fneg_fold_f16:
213 ; GFX9: ; %bb.0:
214 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
215 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
216 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
217 ; GFX9-NEXT: global_load_ushort v1, v0, s[2:3]
218 ; GFX9-NEXT: s_waitcnt vmcnt(0)
219 ; GFX9-NEXT: v_mul_f16_e64 v1, -v1, v1
220 ; GFX9-NEXT: global_store_short v0, v1, s[0:1]
221 ; GFX9-NEXT: s_endpgm
222 ;
223 ; GFX11-LABEL: v_fneg_fold_f16:
224 ; GFX11: ; %bb.0:
225 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
226 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
227 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
228 ; GFX11-NEXT: global_load_u16 v1, v0, s[2:3]
229 ; GFX11-NEXT: s_waitcnt vmcnt(0)
230 ; GFX11-NEXT: v_mul_f16_e64 v1, -v1, v1
231 ; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
232 ; GFX11-NEXT: s_nop 0
233 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
234 ; GFX11-NEXT: s_endpgm
235 %val = load half, ptr addrspace(1) %in
236 %fsub = fsub half -0.0, %val
237 %fmul = fmul half %fsub, %val
238 store half %fmul, ptr addrspace(1) %out
239 ret void
240 }
242 define amdgpu_kernel void @s_fneg_v2f16(ptr addrspace(1) %out, <2 x half> %in) #0 {
243 ; CI-LABEL: s_fneg_v2f16:
244 ; CI: ; %bb.0:
245 ; CI-NEXT: s_load_dword s2, s[4:5], 0x2
246 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
247 ; CI-NEXT: s_waitcnt lgkmcnt(0)
248 ; CI-NEXT: s_xor_b32 s2, s2, 0x80008000
249 ; CI-NEXT: v_mov_b32_e32 v0, s0
250 ; CI-NEXT: v_mov_b32_e32 v1, s1
251 ; CI-NEXT: v_mov_b32_e32 v2, s2
252 ; CI-NEXT: flat_store_dword v[0:1], v2
253 ; CI-NEXT: s_endpgm
254 ;
255 ; GFX8-LABEL: s_fneg_v2f16:
256 ; GFX8: ; %bb.0:
257 ; GFX8-NEXT: s_load_dword s2, s[4:5], 0x8
258 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
259 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
260 ; GFX8-NEXT: s_xor_b32 s2, s2, 0x80008000
261 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
262 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
263 ; GFX8-NEXT: v_mov_b32_e32 v2, s2
264 ; GFX8-NEXT: flat_store_dword v[0:1], v2
265 ; GFX8-NEXT: s_endpgm
266 ;
267 ; GFX9-LABEL: s_fneg_v2f16:
268 ; GFX9: ; %bb.0:
269 ; GFX9-NEXT: s_load_dword s2, s[4:5], 0x8
270 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
271 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
272 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
273 ; GFX9-NEXT: s_xor_b32 s2, s2, 0x80008000
274 ; GFX9-NEXT: v_mov_b32_e32 v1, s2
275 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
276 ; GFX9-NEXT: s_endpgm
277 ;
278 ; GFX11-LABEL: s_fneg_v2f16:
279 ; GFX11: ; %bb.0:
280 ; GFX11-NEXT: s_clause 0x1
281 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x8
282 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
283 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
284 ; GFX11-NEXT: s_xor_b32 s2, s2, 0x80008000
285 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
286 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
287 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
288 ; GFX11-NEXT: s_nop 0
289 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
290 ; GFX11-NEXT: s_endpgm
291 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %in
292 store <2 x half> %fneg, ptr addrspace(1) %out
293 ret void
294 }
296 define amdgpu_kernel void @s_fneg_v2f16_nonload(ptr addrspace(1) %out) #0 {
297 ; CIVI-LABEL: s_fneg_v2f16_nonload:
298 ; CIVI: ; %bb.0:
299 ; CIVI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
300 ; CIVI-NEXT: ;;#ASMSTART
301 ; CIVI-NEXT: ; def s2
302 ; CIVI-NEXT: ;;#ASMEND
303 ; CIVI-NEXT: s_xor_b32 s2, s2, 0x80008000
304 ; CIVI-NEXT: v_mov_b32_e32 v2, s2
305 ; CIVI-NEXT: s_waitcnt lgkmcnt(0)
306 ; CIVI-NEXT: v_mov_b32_e32 v0, s0
307 ; CIVI-NEXT: v_mov_b32_e32 v1, s1
308 ; CIVI-NEXT: flat_store_dword v[0:1], v2
309 ; CIVI-NEXT: s_endpgm
310 ;
311 ; GFX9-LABEL: s_fneg_v2f16_nonload:
312 ; GFX9: ; %bb.0:
313 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
314 ; GFX9-NEXT: ;;#ASMSTART
315 ; GFX9-NEXT: ; def s2
316 ; GFX9-NEXT: ;;#ASMEND
317 ; GFX9-NEXT: s_xor_b32 s2, s2, 0x80008000
318 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
319 ; GFX9-NEXT: v_mov_b32_e32 v1, s2
320 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
321 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
322 ; GFX9-NEXT: s_endpgm
323 ;
324 ; GFX11-LABEL: s_fneg_v2f16_nonload:
325 ; GFX11: ; %bb.0:
326 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
327 ; GFX11-NEXT: ;;#ASMSTART
328 ; GFX11-NEXT: ; def s2
329 ; GFX11-NEXT: ;;#ASMEND
330 ; GFX11-NEXT: s_xor_b32 s2, s2, 0x80008000
331 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
332 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
333 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
334 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
335 ; GFX11-NEXT: s_nop 0
336 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
337 ; GFX11-NEXT: s_endpgm
338 %in = call i32 asm sideeffect "; def $0", "=s"()
339 %in.bc = bitcast i32 %in to <2 x half>
340 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %in.bc
341 store <2 x half> %fneg, ptr addrspace(1) %out
342 ret void
343 }
345 define amdgpu_kernel void @v_fneg_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
346 ; CI-LABEL: v_fneg_v2f16:
347 ; CI: ; %bb.0:
348 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2
349 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
350 ; CI-NEXT: s_waitcnt lgkmcnt(0)
351 ; CI-NEXT: v_mov_b32_e32 v1, s1
352 ; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0
353 ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
354 ; CI-NEXT: flat_load_dword v2, v[0:1]
355 ; CI-NEXT: s_waitcnt vmcnt(0)
356 ; CI-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
357 ; CI-NEXT: flat_store_dword v[0:1], v2
358 ; CI-NEXT: s_endpgm
359 ;
360 ; GFX8-LABEL: v_fneg_v2f16:
361 ; GFX8: ; %bb.0:
362 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
363 ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
364 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
365 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
366 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
367 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
368 ; GFX8-NEXT: flat_load_dword v2, v[0:1]
369 ; GFX8-NEXT: s_waitcnt vmcnt(0)
370 ; GFX8-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
371 ; GFX8-NEXT: flat_store_dword v[0:1], v2
372 ; GFX8-NEXT: s_endpgm
373 ;
374 ; GFX9-LABEL: v_fneg_v2f16:
375 ; GFX9: ; %bb.0:
376 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
377 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
378 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
379 ; GFX9-NEXT: global_load_dword v1, v0, s[0:1]
380 ; GFX9-NEXT: s_waitcnt vmcnt(0)
381 ; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
382 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
383 ; GFX9-NEXT: s_endpgm
384 ;
385 ; GFX11-LABEL: v_fneg_v2f16:
386 ; GFX11: ; %bb.0:
387 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x8
388 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
389 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
390 ; GFX11-NEXT: global_load_b32 v1, v0, s[0:1]
391 ; GFX11-NEXT: s_waitcnt vmcnt(0)
392 ; GFX11-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
393 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
394 ; GFX11-NEXT: s_nop 0
395 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
396 ; GFX11-NEXT: s_endpgm
397 %tid = call i32 @llvm.amdgcn.workitem.id.x()
398 %gep.in = getelementptr inbounds <2 x half>, ptr addrspace(1) %in, i32 %tid
399 %gep.out = getelementptr inbounds <2 x half>, ptr addrspace(1) %in, i32 %tid
400 %val = load <2 x half>, ptr addrspace(1) %gep.in, align 2
401 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %val
402 store <2 x half> %fneg, ptr addrspace(1) %gep.out
403 ret void
404 }
406 define amdgpu_kernel void @fneg_free_v2f16(ptr addrspace(1) %out, i32 %in) #0 {
407 ; CI-LABEL: fneg_free_v2f16:
408 ; CI: ; %bb.0:
409 ; CI-NEXT: s_load_dword s2, s[4:5], 0x2
410 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
411 ; CI-NEXT: s_waitcnt lgkmcnt(0)
412 ; CI-NEXT: s_xor_b32 s2, s2, 0x80008000
413 ; CI-NEXT: v_mov_b32_e32 v0, s0
414 ; CI-NEXT: v_mov_b32_e32 v1, s1
415 ; CI-NEXT: v_mov_b32_e32 v2, s2
416 ; CI-NEXT: flat_store_dword v[0:1], v2
417 ; CI-NEXT: s_endpgm
418 ;
419 ; GFX8-LABEL: fneg_free_v2f16:
420 ; GFX8: ; %bb.0:
421 ; GFX8-NEXT: s_load_dword s2, s[4:5], 0x8
422 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
423 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
424 ; GFX8-NEXT: s_xor_b32 s2, s2, 0x80008000
425 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
426 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
427 ; GFX8-NEXT: v_mov_b32_e32 v2, s2
428 ; GFX8-NEXT: flat_store_dword v[0:1], v2
429 ; GFX8-NEXT: s_endpgm
430 ;
431 ; GFX9-LABEL: fneg_free_v2f16:
432 ; GFX9: ; %bb.0:
433 ; GFX9-NEXT: s_load_dword s2, s[4:5], 0x8
434 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
435 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
436 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
437 ; GFX9-NEXT: s_xor_b32 s2, s2, 0x80008000
438 ; GFX9-NEXT: v_mov_b32_e32 v1, s2
439 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
440 ; GFX9-NEXT: s_endpgm
441 ;
442 ; GFX11-LABEL: fneg_free_v2f16:
443 ; GFX11: ; %bb.0:
444 ; GFX11-NEXT: s_clause 0x1
445 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x8
446 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
447 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
448 ; GFX11-NEXT: s_xor_b32 s2, s2, 0x80008000
449 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
450 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
451 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
452 ; GFX11-NEXT: s_nop 0
453 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
454 ; GFX11-NEXT: s_endpgm
455 %bc = bitcast i32 %in to <2 x half>
456 %fsub = fsub <2 x half> <half -0.0, half -0.0>, %bc
457 store <2 x half> %fsub, ptr addrspace(1) %out
458 ret void
459 }
461 define amdgpu_kernel void @v_fneg_fold_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
462 ; CI-LABEL: v_fneg_fold_v2f16:
463 ; CI: ; %bb.0:
464 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
465 ; CI-NEXT: s_waitcnt lgkmcnt(0)
466 ; CI-NEXT: v_mov_b32_e32 v0, s2
467 ; CI-NEXT: v_mov_b32_e32 v1, s3
468 ; CI-NEXT: flat_load_dword v0, v[0:1]
469 ; CI-NEXT: s_waitcnt vmcnt(0)
470 ; CI-NEXT: v_xor_b32_e32 v2, 0x80008000, v0
471 ; CI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
472 ; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
473 ; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
474 ; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
475 ; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
476 ; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
477 ; CI-NEXT: v_mul_f32_e32 v1, v3, v1
478 ; CI-NEXT: v_cvt_f16_f32_e32 v3, v1
479 ; CI-NEXT: v_mul_f32_e32 v0, v2, v0
480 ; CI-NEXT: v_cvt_f16_f32_e32 v2, v0
481 ; CI-NEXT: v_mov_b32_e32 v0, s0
482 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
483 ; CI-NEXT: v_mov_b32_e32 v1, s1
484 ; CI-NEXT: v_or_b32_e32 v2, v2, v3
485 ; CI-NEXT: flat_store_dword v[0:1], v2
486 ; CI-NEXT: s_endpgm
487 ;
488 ; GFX8-LABEL: v_fneg_fold_v2f16:
489 ; GFX8: ; %bb.0:
490 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
491 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
492 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
493 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
494 ; GFX8-NEXT: flat_load_dword v2, v[0:1]
495 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
496 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
497 ; GFX8-NEXT: s_waitcnt vmcnt(0)
498 ; GFX8-NEXT: v_mul_f16_sdwa v3, -v2, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
499 ; GFX8-NEXT: v_mul_f16_e64 v2, -v2, v2
500 ; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
501 ; GFX8-NEXT: flat_store_dword v[0:1], v2
502 ; GFX8-NEXT: s_endpgm
503 ;
504 ; GFX9-LABEL: v_fneg_fold_v2f16:
505 ; GFX9: ; %bb.0:
506 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
507 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
508 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
509 ; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
510 ; GFX9-NEXT: s_waitcnt vmcnt(0)
511 ; GFX9-NEXT: v_pk_mul_f16 v1, v1, v1 neg_lo:[1,0] neg_hi:[1,0]
512 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
513 ; GFX9-NEXT: s_endpgm
514 ;
515 ; GFX11-LABEL: v_fneg_fold_v2f16:
516 ; GFX11: ; %bb.0:
517 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
518 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
519 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
520 ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
521 ; GFX11-NEXT: s_waitcnt vmcnt(0)
522 ; GFX11-NEXT: v_pk_mul_f16 v1, v1, v1 neg_lo:[1,0] neg_hi:[1,0]
523 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
524 ; GFX11-NEXT: s_nop 0
525 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
526 ; GFX11-NEXT: s_endpgm
527 %val = load <2 x half>, ptr addrspace(1) %in
528 %fsub = fsub <2 x half> <half -0.0, half -0.0>, %val
529 %fmul = fmul <2 x half> %fsub, %val
530 store <2 x half> %fmul, ptr addrspace(1) %out
531 ret void
532 }
534 define amdgpu_kernel void @v_extract_fneg_fold_v2f16(ptr addrspace(1) %in) #0 {
535 ; CI-LABEL: v_extract_fneg_fold_v2f16:
536 ; CI: ; %bb.0:
537 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
538 ; CI-NEXT: s_waitcnt lgkmcnt(0)
539 ; CI-NEXT: v_mov_b32_e32 v0, s0
540 ; CI-NEXT: v_mov_b32_e32 v1, s1
541 ; CI-NEXT: flat_load_dword v0, v[0:1]
542 ; CI-NEXT: s_waitcnt vmcnt(0)
543 ; CI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
544 ; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
545 ; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
546 ; CI-NEXT: v_mul_f32_e32 v0, -4.0, v0
547 ; CI-NEXT: v_sub_f32_e32 v1, 2.0, v1
548 ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
549 ; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
550 ; CI-NEXT: flat_store_short v[0:1], v0
551 ; CI-NEXT: s_waitcnt vmcnt(0)
552 ; CI-NEXT: flat_store_short v[0:1], v1
553 ; CI-NEXT: s_waitcnt vmcnt(0)
554 ; CI-NEXT: s_endpgm
555 ;
556 ; GFX8-LABEL: v_extract_fneg_fold_v2f16:
557 ; GFX8: ; %bb.0:
558 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
559 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
560 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
561 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
562 ; GFX8-NEXT: flat_load_dword v0, v[0:1]
563 ; GFX8-NEXT: v_mov_b32_e32 v1, 0x4000
564 ; GFX8-NEXT: s_waitcnt vmcnt(0)
565 ; GFX8-NEXT: v_mul_f16_e32 v2, -4.0, v0
566 ; GFX8-NEXT: v_sub_f16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
567 ; GFX8-NEXT: flat_store_short v[0:1], v2
568 ; GFX8-NEXT: s_waitcnt vmcnt(0)
569 ; GFX8-NEXT: flat_store_short v[0:1], v0
570 ; GFX8-NEXT: s_waitcnt vmcnt(0)
571 ; GFX8-NEXT: s_endpgm
572 ;
573 ; GFX9-LABEL: v_extract_fneg_fold_v2f16:
574 ; GFX9: ; %bb.0:
575 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
576 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
577 ; GFX9-NEXT: v_mov_b32_e32 v1, 0x4000
578 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
579 ; GFX9-NEXT: global_load_dword v0, v0, s[0:1]
580 ; GFX9-NEXT: s_waitcnt vmcnt(0)
581 ; GFX9-NEXT: v_mul_f16_e32 v2, -4.0, v0
582 ; GFX9-NEXT: v_sub_f16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
583 ; GFX9-NEXT: global_store_short v[0:1], v2, off
584 ; GFX9-NEXT: s_waitcnt vmcnt(0)
585 ; GFX9-NEXT: global_store_short v[0:1], v0, off
586 ; GFX9-NEXT: s_waitcnt vmcnt(0)
587 ; GFX9-NEXT: s_endpgm
588 ;
589 ; GFX11-LABEL: v_extract_fneg_fold_v2f16:
590 ; GFX11: ; %bb.0:
591 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
592 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
593 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
594 ; GFX11-NEXT: global_load_b32 v0, v0, s[0:1]
595 ; GFX11-NEXT: s_waitcnt vmcnt(0)
596 ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
597 ; GFX11-NEXT: v_mul_f16_e32 v0, -4.0, v0
598 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
599 ; GFX11-NEXT: v_sub_f16_e32 v1, 2.0, v1
600 ; GFX11-NEXT: global_store_b16 v[0:1], v0, off dlc
601 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
602 ; GFX11-NEXT: global_store_b16 v[0:1], v1, off dlc
603 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
604 ; GFX11-NEXT: s_nop 0
605 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
606 ; GFX11-NEXT: s_endpgm
607 %val = load <2 x half>, ptr addrspace(1) %in
608 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %val
609 %elt0 = extractelement <2 x half> %fneg, i32 0
610 %elt1 = extractelement <2 x half> %fneg, i32 1
612 %fmul0 = fmul half %elt0, 4.0
613 %fadd1 = fadd half %elt1, 2.0
614 store volatile half %fmul0, ptr addrspace(1) undef
615 store volatile half %fadd1, ptr addrspace(1) undef
616 ret void
617 }
619 define amdgpu_kernel void @v_extract_fneg_no_fold_v2f16(ptr addrspace(1) %in) #0 {
620 ; CIVI-LABEL: v_extract_fneg_no_fold_v2f16:
621 ; CIVI: ; %bb.0:
622 ; CIVI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
623 ; CIVI-NEXT: s_waitcnt lgkmcnt(0)
624 ; CIVI-NEXT: v_mov_b32_e32 v0, s0
625 ; CIVI-NEXT: v_mov_b32_e32 v1, s1
626 ; CIVI-NEXT: flat_load_dword v0, v[0:1]
627 ; CIVI-NEXT: s_waitcnt vmcnt(0)
628 ; CIVI-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
629 ; CIVI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
630 ; CIVI-NEXT: flat_store_short v[0:1], v0
631 ; CIVI-NEXT: s_waitcnt vmcnt(0)
632 ; CIVI-NEXT: flat_store_short v[0:1], v1
633 ; CIVI-NEXT: s_waitcnt vmcnt(0)
634 ; CIVI-NEXT: s_endpgm
635 ;
636 ; GFX9-LABEL: v_extract_fneg_no_fold_v2f16:
637 ; GFX9: ; %bb.0:
638 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
639 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
640 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
641 ; GFX9-NEXT: global_load_dword v0, v0, s[0:1]
642 ; GFX9-NEXT: s_waitcnt vmcnt(0)
643 ; GFX9-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
644 ; GFX9-NEXT: global_store_short v[0:1], v0, off
645 ; GFX9-NEXT: s_waitcnt vmcnt(0)
646 ; GFX9-NEXT: global_store_short_d16_hi v[0:1], v0, off
647 ; GFX9-NEXT: s_waitcnt vmcnt(0)
648 ; GFX9-NEXT: s_endpgm
649 ;
650 ; GFX11-LABEL: v_extract_fneg_no_fold_v2f16:
651 ; GFX11: ; %bb.0:
652 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
653 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
654 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
655 ; GFX11-NEXT: global_load_b32 v0, v0, s[0:1]
656 ; GFX11-NEXT: s_waitcnt vmcnt(0)
657 ; GFX11-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
658 ; GFX11-NEXT: global_store_b16 v[0:1], v0, off dlc
659 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
660 ; GFX11-NEXT: global_store_d16_hi_b16 v[0:1], v0, off dlc
661 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
662 ; GFX11-NEXT: s_nop 0
663 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
664 ; GFX11-NEXT: s_endpgm
665 %val = load <2 x half>, ptr addrspace(1) %in
666 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %val
667 %elt0 = extractelement <2 x half> %fneg, i32 0
668 %elt1 = extractelement <2 x half> %fneg, i32 1
669 store volatile half %elt0, ptr addrspace(1) undef
670 store volatile half %elt1, ptr addrspace(1) undef
671 ret void
672 }
674 declare i32 @llvm.amdgcn.workitem.id.x() #1
676 attributes #0 = { nounwind }
677 attributes #1 = { nounwind readnone }