1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -global-isel=0 -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s -check-prefixes=GFX10,GFX10-SDAG
3 ; RUN: llc < %s -global-isel=0 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck %s -check-prefixes=GFX11,GFX11-SDAG
4 ; RUN: llc < %s -global-isel=1 -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s -check-prefixes=GFX10,GFX10-GISEL
5 ; RUN: llc < %s -global-isel=1 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck %s -check-prefixes=GFX11,GFX11-GISEL
7 declare float @llvm.amdgcn.global.atomic.fmin.f32.p1.f32(ptr addrspace(1) %ptr, float %data)
8 declare float @llvm.amdgcn.global.atomic.fmax.f32.p1.f32(ptr addrspace(1) %ptr, float %data)
10 define amdgpu_cs void @global_atomic_fmin_f32_noret(ptr addrspace(1) %ptr, float %data) {
11 ; GFX10-LABEL: global_atomic_fmin_f32_noret:
13 ; GFX10-NEXT: global_atomic_fmin v[0:1], v2, off
14 ; GFX10-NEXT: s_endpgm
16 ; GFX11-LABEL: global_atomic_fmin_f32_noret:
18 ; GFX11-NEXT: global_atomic_min_f32 v[0:1], v2, off
20 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
21 ; GFX11-NEXT: s_endpgm
22 %ret = call float @llvm.amdgcn.global.atomic.fmin.f32.p1.f32(ptr addrspace(1) %ptr, float %data)
26 define amdgpu_cs void @global_atomic_fmax_f32_noret(ptr addrspace(1) %ptr, float %data) {
27 ; GFX10-LABEL: global_atomic_fmax_f32_noret:
29 ; GFX10-NEXT: global_atomic_fmax v[0:1], v2, off
30 ; GFX10-NEXT: s_endpgm
32 ; GFX11-LABEL: global_atomic_fmax_f32_noret:
34 ; GFX11-NEXT: global_atomic_max_f32 v[0:1], v2, off
36 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
37 ; GFX11-NEXT: s_endpgm
38 %ret = call float @llvm.amdgcn.global.atomic.fmax.f32.p1.f32(ptr addrspace(1) %ptr, float %data)
42 define amdgpu_cs void @global_atomic_fmax_f32_rtn(ptr addrspace(1) %ptr, float %data, ptr addrspace(1) %out) {
43 ; GFX10-LABEL: global_atomic_fmax_f32_rtn:
45 ; GFX10-NEXT: global_atomic_fmax v0, v[0:1], v2, off glc
46 ; GFX10-NEXT: s_waitcnt vmcnt(0)
47 ; GFX10-NEXT: global_store_dword v[3:4], v0, off
48 ; GFX10-NEXT: s_endpgm
50 ; GFX11-LABEL: global_atomic_fmax_f32_rtn:
52 ; GFX11-NEXT: global_atomic_max_f32 v0, v[0:1], v2, off glc
53 ; GFX11-NEXT: s_waitcnt vmcnt(0)
54 ; GFX11-NEXT: global_store_b32 v[3:4], v0, off
56 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
57 ; GFX11-NEXT: s_endpgm
58 %ret = call float @llvm.amdgcn.global.atomic.fmax.f32.p1.f32(ptr addrspace(1) %ptr, float %data)
59 store float %ret, ptr addrspace(1) %out
63 define amdgpu_cs void @global_atomic_fmin_f32_rtn(ptr addrspace(1) %ptr, float %data, ptr addrspace(1) %out) {
64 ; GFX10-LABEL: global_atomic_fmin_f32_rtn:
66 ; GFX10-NEXT: global_atomic_fmin v0, v[0:1], v2, off glc
67 ; GFX10-NEXT: s_waitcnt vmcnt(0)
68 ; GFX10-NEXT: global_store_dword v[3:4], v0, off
69 ; GFX10-NEXT: s_endpgm
71 ; GFX11-LABEL: global_atomic_fmin_f32_rtn:
73 ; GFX11-NEXT: global_atomic_min_f32 v0, v[0:1], v2, off glc
74 ; GFX11-NEXT: s_waitcnt vmcnt(0)
75 ; GFX11-NEXT: global_store_b32 v[3:4], v0, off
77 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
78 ; GFX11-NEXT: s_endpgm
79 %ret = call float @llvm.amdgcn.global.atomic.fmin.f32.p1.f32(ptr addrspace(1) %ptr, float %data)
80 store float %ret, ptr addrspace(1) %out
83 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: