| blob | 76c40f5962c58891f67a297a6f9cc6e27fa73374 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s --check-prefixes=SI
3 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s --check-prefixes=VI
4 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s --check-prefixes=EG
6 declare float @llvm.fabs.f32(float) #1
8 define amdgpu_kernel void @fp_to_sint_i32(ptr addrspace(1) %out, float %in) {
9 ; SI-LABEL: fp_to_sint_i32:
10 ; SI: ; %bb.0:
11 ; SI-NEXT: s_load_dword s4, s[0:1], 0xb
12 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
13 ; SI-NEXT: s_mov_b32 s3, 0xf000
14 ; SI-NEXT: s_mov_b32 s2, -1
15 ; SI-NEXT: s_waitcnt lgkmcnt(0)
16 ; SI-NEXT: v_cvt_i32_f32_e32 v0, s4
17 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
18 ; SI-NEXT: s_endpgm
19 ;
20 ; VI-LABEL: fp_to_sint_i32:
21 ; VI: ; %bb.0:
22 ; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
23 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
24 ; VI-NEXT: s_mov_b32 s3, 0xf000
25 ; VI-NEXT: s_waitcnt lgkmcnt(0)
26 ; VI-NEXT: v_cvt_i32_f32_e32 v0, s2
27 ; VI-NEXT: s_mov_b32 s2, -1
28 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
29 ; VI-NEXT: s_endpgm
30 ;
31 ; EG-LABEL: fp_to_sint_i32:
32 ; EG: ; %bb.0:
33 ; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
34 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
35 ; EG-NEXT: CF_END
36 ; EG-NEXT: PAD
37 ; EG-NEXT: ALU clause starting at 4:
38 ; EG-NEXT: TRUNC * T0.W, KC0[2].Z,
39 ; EG-NEXT: FLT_TO_INT T0.X, PV.W,
40 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
41 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
42 %conv = fptosi float %in to i32
43 store i32 %conv, ptr addrspace(1) %out
44 ret void
45 }
47 define amdgpu_kernel void @fp_to_sint_i32_fabs(ptr addrspace(1) %out, float %in) {
48 ; SI-LABEL: fp_to_sint_i32_fabs:
49 ; SI: ; %bb.0:
50 ; SI-NEXT: s_load_dword s4, s[0:1], 0xb
51 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
52 ; SI-NEXT: s_mov_b32 s3, 0xf000
53 ; SI-NEXT: s_mov_b32 s2, -1
54 ; SI-NEXT: s_waitcnt lgkmcnt(0)
55 ; SI-NEXT: v_cvt_i32_f32_e64 v0, |s4|
56 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
57 ; SI-NEXT: s_endpgm
58 ;
59 ; VI-LABEL: fp_to_sint_i32_fabs:
60 ; VI: ; %bb.0:
61 ; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
62 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
63 ; VI-NEXT: s_mov_b32 s3, 0xf000
64 ; VI-NEXT: s_waitcnt lgkmcnt(0)
65 ; VI-NEXT: v_cvt_i32_f32_e64 v0, |s2|
66 ; VI-NEXT: s_mov_b32 s2, -1
67 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
68 ; VI-NEXT: s_endpgm
69 ;
70 ; EG-LABEL: fp_to_sint_i32_fabs:
71 ; EG: ; %bb.0:
72 ; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
73 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
74 ; EG-NEXT: CF_END
75 ; EG-NEXT: PAD
76 ; EG-NEXT: ALU clause starting at 4:
77 ; EG-NEXT: TRUNC * T0.W, |KC0[2].Z|,
78 ; EG-NEXT: FLT_TO_INT T0.X, PV.W,
79 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
80 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
81 %in.fabs = call float @llvm.fabs.f32(float %in)
82 %conv = fptosi float %in.fabs to i32
83 store i32 %conv, ptr addrspace(1) %out
84 ret void
85 }
87 define amdgpu_kernel void @fp_to_sint_v2i32(ptr addrspace(1) %out, <2 x float> %in) {
88 ; SI-LABEL: fp_to_sint_v2i32:
89 ; SI: ; %bb.0:
90 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
91 ; SI-NEXT: s_mov_b32 s7, 0xf000
92 ; SI-NEXT: s_mov_b32 s6, -1
93 ; SI-NEXT: s_waitcnt lgkmcnt(0)
94 ; SI-NEXT: s_mov_b32 s4, s0
95 ; SI-NEXT: s_mov_b32 s5, s1
96 ; SI-NEXT: v_cvt_i32_f32_e32 v1, s3
97 ; SI-NEXT: v_cvt_i32_f32_e32 v0, s2
98 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
99 ; SI-NEXT: s_endpgm
100 ;
101 ; VI-LABEL: fp_to_sint_v2i32:
102 ; VI: ; %bb.0:
103 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
104 ; VI-NEXT: s_mov_b32 s7, 0xf000
105 ; VI-NEXT: s_mov_b32 s6, -1
106 ; VI-NEXT: s_waitcnt lgkmcnt(0)
107 ; VI-NEXT: v_cvt_i32_f32_e32 v1, s3
108 ; VI-NEXT: v_cvt_i32_f32_e32 v0, s2
109 ; VI-NEXT: s_mov_b32 s4, s0
110 ; VI-NEXT: s_mov_b32 s5, s1
111 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
112 ; VI-NEXT: s_endpgm
113 ;
114 ; EG-LABEL: fp_to_sint_v2i32:
115 ; EG: ; %bb.0:
116 ; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
117 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
118 ; EG-NEXT: CF_END
119 ; EG-NEXT: PAD
120 ; EG-NEXT: ALU clause starting at 4:
121 ; EG-NEXT: TRUNC * T0.W, KC0[3].X,
122 ; EG-NEXT: FLT_TO_INT T0.Y, PV.W,
123 ; EG-NEXT: TRUNC * T0.W, KC0[2].W,
124 ; EG-NEXT: FLT_TO_INT T0.X, PV.W,
125 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
126 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
127 %result = fptosi <2 x float> %in to <2 x i32>
128 store <2 x i32> %result, ptr addrspace(1) %out
129 ret void
130 }
132 define amdgpu_kernel void @fp_to_sint_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
133 ; SI-LABEL: fp_to_sint_v4i32:
134 ; SI: ; %bb.0:
135 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
136 ; SI-NEXT: s_waitcnt lgkmcnt(0)
137 ; SI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
138 ; SI-NEXT: s_mov_b32 s3, 0xf000
139 ; SI-NEXT: s_mov_b32 s2, -1
140 ; SI-NEXT: s_waitcnt lgkmcnt(0)
141 ; SI-NEXT: v_cvt_i32_f32_e32 v3, s7
142 ; SI-NEXT: v_cvt_i32_f32_e32 v2, s6
143 ; SI-NEXT: v_cvt_i32_f32_e32 v1, s5
144 ; SI-NEXT: v_cvt_i32_f32_e32 v0, s4
145 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
146 ; SI-NEXT: s_endpgm
147 ;
148 ; VI-LABEL: fp_to_sint_v4i32:
149 ; VI: ; %bb.0:
150 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
151 ; VI-NEXT: s_waitcnt lgkmcnt(0)
152 ; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
153 ; VI-NEXT: s_mov_b32 s3, 0xf000
154 ; VI-NEXT: s_mov_b32 s2, -1
155 ; VI-NEXT: s_waitcnt lgkmcnt(0)
156 ; VI-NEXT: v_cvt_i32_f32_e32 v3, s7
157 ; VI-NEXT: v_cvt_i32_f32_e32 v2, s6
158 ; VI-NEXT: v_cvt_i32_f32_e32 v1, s5
159 ; VI-NEXT: v_cvt_i32_f32_e32 v0, s4
160 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
161 ; VI-NEXT: s_endpgm
162 ;
163 ; EG-LABEL: fp_to_sint_v4i32:
164 ; EG: ; %bb.0:
165 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
166 ; EG-NEXT: TEX 0 @6
167 ; EG-NEXT: ALU 9, @9, KC0[CB0:0-32], KC1[]
168 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
169 ; EG-NEXT: CF_END
170 ; EG-NEXT: PAD
171 ; EG-NEXT: Fetch clause starting at 6:
172 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
173 ; EG-NEXT: ALU clause starting at 8:
174 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
175 ; EG-NEXT: ALU clause starting at 9:
176 ; EG-NEXT: TRUNC T0.W, T0.W,
177 ; EG-NEXT: TRUNC * T1.W, T0.Z,
178 ; EG-NEXT: FLT_TO_INT * T0.W, PV.W,
179 ; EG-NEXT: FLT_TO_INT T0.Z, T1.W,
180 ; EG-NEXT: TRUNC * T1.W, T0.Y,
181 ; EG-NEXT: FLT_TO_INT T0.Y, PV.W,
182 ; EG-NEXT: TRUNC * T1.W, T0.X,
183 ; EG-NEXT: FLT_TO_INT T0.X, PV.W,
184 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
185 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
186 %value = load <4 x float>, ptr addrspace(1) %in
187 %result = fptosi <4 x float> %value to <4 x i32>
188 store <4 x i32> %result, ptr addrspace(1) %out
189 ret void
190 }
192 ; Check that the compiler doesn't crash with a "cannot select" error
193 define amdgpu_kernel void @fp_to_sint_i64 (ptr addrspace(1) %out, float %in) {
194 ; SI-LABEL: fp_to_sint_i64:
195 ; SI: ; %bb.0: ; %entry
196 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
197 ; SI-NEXT: s_load_dword s0, s[0:1], 0xb
198 ; SI-NEXT: s_mov_b32 s7, 0xf000
199 ; SI-NEXT: s_mov_b32 s6, -1
200 ; SI-NEXT: s_mov_b32 s1, 0x2f800000
201 ; SI-NEXT: s_mov_b32 s2, 0xcf800000
202 ; SI-NEXT: s_waitcnt lgkmcnt(0)
203 ; SI-NEXT: v_trunc_f32_e32 v0, s0
204 ; SI-NEXT: v_mul_f32_e64 v1, |v0|, s1
205 ; SI-NEXT: v_ashrrev_i32_e32 v2, 31, v0
206 ; SI-NEXT: v_floor_f32_e32 v1, v1
207 ; SI-NEXT: v_cvt_u32_f32_e32 v3, v1
208 ; SI-NEXT: v_fma_f32 v0, v1, s2, |v0|
209 ; SI-NEXT: v_cvt_u32_f32_e32 v0, v0
210 ; SI-NEXT: v_xor_b32_e32 v1, v3, v2
211 ; SI-NEXT: v_xor_b32_e32 v0, v0, v2
212 ; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
213 ; SI-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
214 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
215 ; SI-NEXT: s_endpgm
216 ;
217 ; VI-LABEL: fp_to_sint_i64:
218 ; VI: ; %bb.0: ; %entry
219 ; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
220 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
221 ; VI-NEXT: s_mov_b32 s4, 0x2f800000
222 ; VI-NEXT: s_mov_b32 s5, 0xcf800000
223 ; VI-NEXT: s_mov_b32 s3, 0xf000
224 ; VI-NEXT: s_waitcnt lgkmcnt(0)
225 ; VI-NEXT: v_trunc_f32_e32 v0, s2
226 ; VI-NEXT: v_mul_f32_e64 v1, |v0|, s4
227 ; VI-NEXT: v_floor_f32_e32 v1, v1
228 ; VI-NEXT: v_fma_f32 v2, v1, s5, |v0|
229 ; VI-NEXT: v_cvt_u32_f32_e32 v2, v2
230 ; VI-NEXT: v_cvt_u32_f32_e32 v1, v1
231 ; VI-NEXT: v_ashrrev_i32_e32 v3, 31, v0
232 ; VI-NEXT: s_mov_b32 s2, -1
233 ; VI-NEXT: v_xor_b32_e32 v0, v2, v3
234 ; VI-NEXT: v_xor_b32_e32 v1, v1, v3
235 ; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v3
236 ; VI-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
237 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
238 ; VI-NEXT: s_endpgm
239 ;
240 ; EG-LABEL: fp_to_sint_i64:
241 ; EG: ; %bb.0: ; %entry
242 ; EG-NEXT: ALU 40, @4, KC0[CB0:0-32], KC1[]
243 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
244 ; EG-NEXT: CF_END
245 ; EG-NEXT: PAD
246 ; EG-NEXT: ALU clause starting at 4:
247 ; EG-NEXT: MOV * T0.W, literal.x,
248 ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
249 ; EG-NEXT: BFE_UINT T0.W, KC0[2].Z, literal.x, PV.W,
250 ; EG-NEXT: AND_INT * T1.W, KC0[2].Z, literal.y,
251 ; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
252 ; EG-NEXT: OR_INT T1.W, PS, literal.x,
253 ; EG-NEXT: ADD_INT * T2.W, PV.W, literal.y,
254 ; EG-NEXT: 8388608(1.175494e-38), -150(nan)
255 ; EG-NEXT: ADD_INT T0.X, T0.W, literal.x,
256 ; EG-NEXT: SUB_INT T0.Y, literal.y, T0.W,
257 ; EG-NEXT: AND_INT T0.Z, PS, literal.z,
258 ; EG-NEXT: NOT_INT T0.W, PS,
259 ; EG-NEXT: LSHR * T3.W, PV.W, 1,
260 ; EG-NEXT: -127(nan), 150(2.101948e-43)
261 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
262 ; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, PS, PV.W,
263 ; EG-NEXT: LSHL T1.Y, T1.W, PV.Z,
264 ; EG-NEXT: AND_INT T0.Z, T2.W, literal.x, BS:VEC_120/SCL_212
265 ; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122
266 ; EG-NEXT: AND_INT * T1.W, PV.Y, literal.x,
267 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
268 ; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,
269 ; EG-NEXT: CNDE_INT T1.Z, PV.Z, PV.Y, 0.0,
270 ; EG-NEXT: CNDE_INT T0.W, PV.Z, PV.X, PV.Y,
271 ; EG-NEXT: SETGT_INT * T1.W, T0.X, literal.x,
272 ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
273 ; EG-NEXT: CNDE_INT T0.Z, PS, 0.0, PV.W,
274 ; EG-NEXT: CNDE_INT T0.W, PS, PV.Y, PV.Z,
275 ; EG-NEXT: ASHR * T1.W, KC0[2].Z, literal.x,
276 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
277 ; EG-NEXT: XOR_INT T0.W, PV.W, PS,
278 ; EG-NEXT: XOR_INT * T2.W, PV.Z, PS,
279 ; EG-NEXT: SUB_INT T2.W, PS, T1.W,
280 ; EG-NEXT: SUBB_UINT * T3.W, PV.W, T1.W,
281 ; EG-NEXT: SUB_INT T2.W, PV.W, PS,
282 ; EG-NEXT: SETGT_INT * T3.W, 0.0, T0.X,
283 ; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,
284 ; EG-NEXT: SUB_INT * T0.W, T0.W, T1.W,
285 ; EG-NEXT: CNDE_INT T0.X, T3.W, PV.W, 0.0,
286 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
287 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
288 entry:
289 %0 = fptosi float %in to i64
290 store i64 %0, ptr addrspace(1) %out
291 ret void
292 }
294 define amdgpu_kernel void @fp_to_sint_v2i64(ptr addrspace(1) %out, <2 x float> %x) {
295 ; SI-LABEL: fp_to_sint_v2i64:
296 ; SI: ; %bb.0:
297 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
298 ; SI-NEXT: s_mov_b32 s3, 0xf000
299 ; SI-NEXT: s_mov_b32 s2, -1
300 ; SI-NEXT: s_mov_b32 s8, 0x2f800000
301 ; SI-NEXT: s_mov_b32 s9, 0xcf800000
302 ; SI-NEXT: s_waitcnt lgkmcnt(0)
303 ; SI-NEXT: s_mov_b32 s0, s4
304 ; SI-NEXT: s_mov_b32 s1, s5
305 ; SI-NEXT: v_trunc_f32_e32 v0, s7
306 ; SI-NEXT: v_trunc_f32_e32 v1, s6
307 ; SI-NEXT: v_mul_f32_e64 v2, |v0|, s8
308 ; SI-NEXT: v_ashrrev_i32_e32 v3, 31, v0
309 ; SI-NEXT: v_mul_f32_e64 v4, |v1|, s8
310 ; SI-NEXT: v_ashrrev_i32_e32 v5, 31, v1
311 ; SI-NEXT: v_floor_f32_e32 v2, v2
312 ; SI-NEXT: v_floor_f32_e32 v4, v4
313 ; SI-NEXT: v_cvt_u32_f32_e32 v6, v2
314 ; SI-NEXT: v_fma_f32 v0, v2, s9, |v0|
315 ; SI-NEXT: v_cvt_u32_f32_e32 v2, v4
316 ; SI-NEXT: v_fma_f32 v1, v4, s9, |v1|
317 ; SI-NEXT: v_cvt_u32_f32_e32 v0, v0
318 ; SI-NEXT: v_xor_b32_e32 v4, v6, v3
319 ; SI-NEXT: v_cvt_u32_f32_e32 v1, v1
320 ; SI-NEXT: v_xor_b32_e32 v6, v2, v5
321 ; SI-NEXT: v_xor_b32_e32 v0, v0, v3
322 ; SI-NEXT: v_xor_b32_e32 v1, v1, v5
323 ; SI-NEXT: v_sub_i32_e32 v2, vcc, v0, v3
324 ; SI-NEXT: v_subb_u32_e32 v3, vcc, v4, v3, vcc
325 ; SI-NEXT: v_sub_i32_e32 v0, vcc, v1, v5
326 ; SI-NEXT: v_subb_u32_e32 v1, vcc, v6, v5, vcc
327 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
328 ; SI-NEXT: s_endpgm
329 ;
330 ; VI-LABEL: fp_to_sint_v2i64:
331 ; VI: ; %bb.0:
332 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
333 ; VI-NEXT: s_mov_b32 s8, 0x2f800000
334 ; VI-NEXT: s_mov_b32 s7, 0xf000
335 ; VI-NEXT: s_mov_b32 s6, -1
336 ; VI-NEXT: s_waitcnt lgkmcnt(0)
337 ; VI-NEXT: v_trunc_f32_e32 v0, s3
338 ; VI-NEXT: v_mul_f32_e64 v1, |v0|, s8
339 ; VI-NEXT: s_mov_b32 s4, s0
340 ; VI-NEXT: v_floor_f32_e32 v1, v1
341 ; VI-NEXT: s_mov_b32 s0, 0xcf800000
342 ; VI-NEXT: v_fma_f32 v2, v1, s0, |v0|
343 ; VI-NEXT: v_trunc_f32_e32 v4, s2
344 ; VI-NEXT: v_cvt_u32_f32_e32 v2, v2
345 ; VI-NEXT: v_mul_f32_e64 v3, |v4|, s8
346 ; VI-NEXT: v_cvt_u32_f32_e32 v1, v1
347 ; VI-NEXT: v_floor_f32_e32 v3, v3
348 ; VI-NEXT: v_cvt_u32_f32_e32 v5, v3
349 ; VI-NEXT: v_fma_f32 v3, v3, s0, |v4|
350 ; VI-NEXT: v_ashrrev_i32_e32 v0, 31, v0
351 ; VI-NEXT: v_cvt_u32_f32_e32 v6, v3
352 ; VI-NEXT: v_xor_b32_e32 v2, v2, v0
353 ; VI-NEXT: v_xor_b32_e32 v1, v1, v0
354 ; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v0
355 ; VI-NEXT: v_subb_u32_e32 v3, vcc, v1, v0, vcc
356 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v4
357 ; VI-NEXT: v_xor_b32_e32 v0, v6, v1
358 ; VI-NEXT: v_xor_b32_e32 v4, v5, v1
359 ; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v1
360 ; VI-NEXT: s_mov_b32 s5, s1
361 ; VI-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc
362 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
363 ; VI-NEXT: s_endpgm
364 ;
365 ; EG-LABEL: fp_to_sint_v2i64:
366 ; EG: ; %bb.0:
367 ; EG-NEXT: ALU 75, @4, KC0[CB0:0-32], KC1[]
368 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
369 ; EG-NEXT: CF_END
370 ; EG-NEXT: PAD
371 ; EG-NEXT: ALU clause starting at 4:
372 ; EG-NEXT: MOV * T0.W, literal.x,
373 ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
374 ; EG-NEXT: BFE_UINT * T1.W, KC0[2].W, literal.x, PV.W,
375 ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
376 ; EG-NEXT: AND_INT T0.Z, KC0[2].W, literal.x,
377 ; EG-NEXT: BFE_UINT T0.W, KC0[3].X, literal.y, T0.W,
378 ; EG-NEXT: ADD_INT * T2.W, PV.W, literal.z,
379 ; EG-NEXT: 8388607(1.175494e-38), 23(3.222986e-44)
380 ; EG-NEXT: -150(nan), 0(0.000000e+00)
381 ; EG-NEXT: SUB_INT T0.X, literal.x, PV.W,
382 ; EG-NEXT: SUB_INT T0.Y, literal.x, T1.W,
383 ; EG-NEXT: AND_INT T1.Z, PS, literal.y,
384 ; EG-NEXT: OR_INT T3.W, PV.Z, literal.z,
385 ; EG-NEXT: AND_INT * T4.W, KC0[3].X, literal.w,
386 ; EG-NEXT: 150(2.101948e-43), 31(4.344025e-44)
387 ; EG-NEXT: 8388608(1.175494e-38), 8388607(1.175494e-38)
388 ; EG-NEXT: OR_INT T1.X, PS, literal.x,
389 ; EG-NEXT: LSHL T1.Y, PV.W, PV.Z,
390 ; EG-NEXT: AND_INT T0.Z, T2.W, literal.y,
391 ; EG-NEXT: BIT_ALIGN_INT T4.W, 0.0, PV.W, PV.Y,
392 ; EG-NEXT: AND_INT * T5.W, PV.Y, literal.y,
393 ; EG-NEXT: 8388608(1.175494e-38), 32(4.484155e-44)
394 ; EG-NEXT: CNDE_INT T2.X, PS, PV.W, 0.0,
395 ; EG-NEXT: CNDE_INT T0.Y, PV.Z, PV.Y, 0.0,
396 ; EG-NEXT: ADD_INT T1.Z, T0.W, literal.x,
397 ; EG-NEXT: BIT_ALIGN_INT T4.W, 0.0, PV.X, T0.X,
398 ; EG-NEXT: AND_INT * T5.W, T0.X, literal.y,
399 ; EG-NEXT: -150(nan), 32(4.484155e-44)
400 ; EG-NEXT: CNDE_INT T0.X, PS, PV.W, 0.0,
401 ; EG-NEXT: NOT_INT T2.Y, T2.W,
402 ; EG-NEXT: AND_INT T2.Z, PV.Z, literal.x,
403 ; EG-NEXT: NOT_INT T2.W, PV.Z,
404 ; EG-NEXT: LSHR * T4.W, T1.X, 1,
405 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
406 ; EG-NEXT: LSHR T3.X, T3.W, 1,
407 ; EG-NEXT: ADD_INT T3.Y, T0.W, literal.x, BS:VEC_120/SCL_212
408 ; EG-NEXT: BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W,
409 ; EG-NEXT: LSHL T0.W, T1.X, PV.Z,
410 ; EG-NEXT: AND_INT * T2.W, T1.Z, literal.y,
411 ; EG-NEXT: -127(nan), 32(4.484155e-44)
412 ; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0,
413 ; EG-NEXT: CNDE_INT T4.Y, PS, PV.Z, PV.W,
414 ; EG-NEXT: SETGT_INT T1.Z, PV.Y, literal.x,
415 ; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, PV.X, T2.Y,
416 ; EG-NEXT: ADD_INT * T1.W, T1.W, literal.y,
417 ; EG-NEXT: 23(3.222986e-44), -127(nan)
418 ; EG-NEXT: CNDE_INT T3.X, T0.Z, PV.W, T1.Y,
419 ; EG-NEXT: SETGT_INT T1.Y, PS, literal.x,
420 ; EG-NEXT: CNDE_INT T0.Z, PV.Z, 0.0, PV.Y,
421 ; EG-NEXT: CNDE_INT T0.W, PV.Z, T0.X, PV.X,
422 ; EG-NEXT: ASHR * T2.W, KC0[3].X, literal.y,
423 ; EG-NEXT: 23(3.222986e-44), 31(4.344025e-44)
424 ; EG-NEXT: XOR_INT T0.X, PV.W, PS,
425 ; EG-NEXT: XOR_INT T2.Y, PV.Z, PS,
426 ; EG-NEXT: CNDE_INT T0.Z, PV.Y, 0.0, PV.X,
427 ; EG-NEXT: CNDE_INT T0.W, PV.Y, T2.X, T0.Y,
428 ; EG-NEXT: ASHR * T3.W, KC0[2].W, literal.x,
429 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
430 ; EG-NEXT: XOR_INT T0.Y, PV.W, PS,
431 ; EG-NEXT: XOR_INT T0.Z, PV.Z, PS,
432 ; EG-NEXT: SUB_INT T0.W, PV.Y, T2.W,
433 ; EG-NEXT: SUBB_UINT * T4.W, PV.X, T2.W,
434 ; EG-NEXT: SUB_INT T1.Y, PV.W, PS,
435 ; EG-NEXT: SETGT_INT T1.Z, 0.0, T3.Y,
436 ; EG-NEXT: SUB_INT T0.W, PV.Z, T3.W,
437 ; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T3.W,
438 ; EG-NEXT: SUB_INT T0.Z, PV.W, PS,
439 ; EG-NEXT: SETGT_INT T0.W, 0.0, T1.W,
440 ; EG-NEXT: CNDE_INT * T1.W, PV.Z, PV.Y, 0.0,
441 ; EG-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, 0.0,
442 ; EG-NEXT: SUB_INT * T2.W, T0.X, T2.W,
443 ; EG-NEXT: CNDE_INT T1.Z, T1.Z, PV.W, 0.0,
444 ; EG-NEXT: SUB_INT * T2.W, T0.Y, T3.W,
445 ; EG-NEXT: CNDE_INT T1.X, T0.W, PV.W, 0.0,
446 ; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
447 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
448 %conv = fptosi <2 x float> %x to <2 x i64>
449 store <2 x i64> %conv, ptr addrspace(1) %out
450 ret void
451 }
453 define amdgpu_kernel void @fp_to_sint_v4i64(ptr addrspace(1) %out, <4 x float> %x) {
454 ; SI-LABEL: fp_to_sint_v4i64:
455 ; SI: ; %bb.0:
456 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
457 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
458 ; SI-NEXT: s_mov_b32 s7, 0xf000
459 ; SI-NEXT: s_mov_b32 s6, -1
460 ; SI-NEXT: s_mov_b32 s8, 0x2f800000
461 ; SI-NEXT: s_mov_b32 s9, 0xcf800000
462 ; SI-NEXT: s_waitcnt lgkmcnt(0)
463 ; SI-NEXT: v_trunc_f32_e32 v0, s1
464 ; SI-NEXT: v_trunc_f32_e32 v1, s0
465 ; SI-NEXT: v_trunc_f32_e32 v2, s3
466 ; SI-NEXT: v_trunc_f32_e32 v3, s2
467 ; SI-NEXT: v_mul_f32_e64 v4, |v0|, s8
468 ; SI-NEXT: v_ashrrev_i32_e32 v5, 31, v0
469 ; SI-NEXT: v_mul_f32_e64 v6, |v1|, s8
470 ; SI-NEXT: v_ashrrev_i32_e32 v7, 31, v1
471 ; SI-NEXT: v_mul_f32_e64 v8, |v2|, s8
472 ; SI-NEXT: v_ashrrev_i32_e32 v9, 31, v2
473 ; SI-NEXT: v_mul_f32_e64 v10, |v3|, s8
474 ; SI-NEXT: v_ashrrev_i32_e32 v11, 31, v3
475 ; SI-NEXT: v_floor_f32_e32 v4, v4
476 ; SI-NEXT: v_floor_f32_e32 v6, v6
477 ; SI-NEXT: v_floor_f32_e32 v8, v8
478 ; SI-NEXT: v_floor_f32_e32 v10, v10
479 ; SI-NEXT: v_cvt_u32_f32_e32 v12, v4
480 ; SI-NEXT: v_fma_f32 v0, v4, s9, |v0|
481 ; SI-NEXT: v_cvt_u32_f32_e32 v4, v6
482 ; SI-NEXT: v_fma_f32 v1, v6, s9, |v1|
483 ; SI-NEXT: v_cvt_u32_f32_e32 v6, v8
484 ; SI-NEXT: v_fma_f32 v2, v8, s9, |v2|
485 ; SI-NEXT: v_cvt_u32_f32_e32 v8, v10
486 ; SI-NEXT: v_fma_f32 v3, v10, s9, |v3|
487 ; SI-NEXT: v_cvt_u32_f32_e32 v0, v0
488 ; SI-NEXT: v_xor_b32_e32 v10, v12, v5
489 ; SI-NEXT: v_cvt_u32_f32_e32 v1, v1
490 ; SI-NEXT: v_xor_b32_e32 v4, v4, v7
491 ; SI-NEXT: v_cvt_u32_f32_e32 v2, v2
492 ; SI-NEXT: v_xor_b32_e32 v12, v6, v9
493 ; SI-NEXT: v_cvt_u32_f32_e32 v3, v3
494 ; SI-NEXT: v_xor_b32_e32 v8, v8, v11
495 ; SI-NEXT: v_xor_b32_e32 v0, v0, v5
496 ; SI-NEXT: v_xor_b32_e32 v1, v1, v7
497 ; SI-NEXT: v_xor_b32_e32 v6, v2, v9
498 ; SI-NEXT: v_xor_b32_e32 v13, v3, v11
499 ; SI-NEXT: v_sub_i32_e32 v2, vcc, v0, v5
500 ; SI-NEXT: v_subb_u32_e32 v3, vcc, v10, v5, vcc
501 ; SI-NEXT: v_sub_i32_e32 v0, vcc, v1, v7
502 ; SI-NEXT: v_subb_u32_e32 v1, vcc, v4, v7, vcc
503 ; SI-NEXT: v_sub_i32_e32 v6, vcc, v6, v9
504 ; SI-NEXT: v_subb_u32_e32 v7, vcc, v12, v9, vcc
505 ; SI-NEXT: v_sub_i32_e32 v4, vcc, v13, v11
506 ; SI-NEXT: v_subb_u32_e32 v5, vcc, v8, v11, vcc
507 ; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
508 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
509 ; SI-NEXT: s_endpgm
510 ;
511 ; VI-LABEL: fp_to_sint_v4i64:
512 ; VI: ; %bb.0:
513 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
514 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
515 ; VI-NEXT: s_mov_b32 s8, 0x2f800000
516 ; VI-NEXT: s_mov_b32 s9, 0xcf800000
517 ; VI-NEXT: s_mov_b32 s3, 0xf000
518 ; VI-NEXT: s_waitcnt lgkmcnt(0)
519 ; VI-NEXT: v_trunc_f32_e32 v0, s5
520 ; VI-NEXT: v_mul_f32_e64 v1, |v0|, s8
521 ; VI-NEXT: v_floor_f32_e32 v1, v1
522 ; VI-NEXT: v_fma_f32 v2, v1, s9, |v0|
523 ; VI-NEXT: v_cvt_u32_f32_e32 v2, v2
524 ; VI-NEXT: v_trunc_f32_e32 v4, s4
525 ; VI-NEXT: v_cvt_u32_f32_e32 v1, v1
526 ; VI-NEXT: v_mul_f32_e64 v3, |v4|, s8
527 ; VI-NEXT: v_floor_f32_e32 v3, v3
528 ; VI-NEXT: v_ashrrev_i32_e32 v0, 31, v0
529 ; VI-NEXT: v_cvt_u32_f32_e32 v5, v3
530 ; VI-NEXT: v_fma_f32 v3, v3, s9, |v4|
531 ; VI-NEXT: v_xor_b32_e32 v2, v2, v0
532 ; VI-NEXT: v_cvt_u32_f32_e32 v6, v3
533 ; VI-NEXT: v_xor_b32_e32 v1, v1, v0
534 ; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v0
535 ; VI-NEXT: v_subb_u32_e32 v3, vcc, v1, v0, vcc
536 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v4
537 ; VI-NEXT: v_xor_b32_e32 v4, v5, v1
538 ; VI-NEXT: v_trunc_f32_e32 v5, s7
539 ; VI-NEXT: v_xor_b32_e32 v0, v6, v1
540 ; VI-NEXT: v_mul_f32_e64 v6, |v5|, s8
541 ; VI-NEXT: v_floor_f32_e32 v6, v6
542 ; VI-NEXT: v_cvt_u32_f32_e32 v7, v6
543 ; VI-NEXT: v_fma_f32 v6, v6, s9, |v5|
544 ; VI-NEXT: v_cvt_u32_f32_e32 v6, v6
545 ; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v1
546 ; VI-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc
547 ; VI-NEXT: v_ashrrev_i32_e32 v4, 31, v5
548 ; VI-NEXT: v_trunc_f32_e32 v8, s6
549 ; VI-NEXT: v_xor_b32_e32 v5, v6, v4
550 ; VI-NEXT: v_mul_f32_e64 v6, |v8|, s8
551 ; VI-NEXT: v_floor_f32_e32 v6, v6
552 ; VI-NEXT: v_cvt_u32_f32_e32 v9, v6
553 ; VI-NEXT: v_fma_f32 v6, v6, s9, |v8|
554 ; VI-NEXT: v_cvt_u32_f32_e32 v10, v6
555 ; VI-NEXT: v_xor_b32_e32 v7, v7, v4
556 ; VI-NEXT: v_sub_u32_e32 v6, vcc, v5, v4
557 ; VI-NEXT: v_ashrrev_i32_e32 v5, 31, v8
558 ; VI-NEXT: v_subb_u32_e32 v7, vcc, v7, v4, vcc
559 ; VI-NEXT: v_xor_b32_e32 v4, v10, v5
560 ; VI-NEXT: v_xor_b32_e32 v8, v9, v5
561 ; VI-NEXT: v_sub_u32_e32 v4, vcc, v4, v5
562 ; VI-NEXT: s_mov_b32 s2, -1
563 ; VI-NEXT: v_subb_u32_e32 v5, vcc, v8, v5, vcc
564 ; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
565 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
566 ; VI-NEXT: s_endpgm
567 ;
568 ; EG-LABEL: fp_to_sint_v4i64:
569 ; EG: ; %bb.0:
570 ; EG-NEXT: ALU 101, @6, KC0[CB0:0-32], KC1[]
571 ; EG-NEXT: ALU 54, @108, KC0[CB0:0-32], KC1[]
572 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 0
573 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T2.X, 1
574 ; EG-NEXT: CF_END
575 ; EG-NEXT: PAD
576 ; EG-NEXT: ALU clause starting at 6:
577 ; EG-NEXT: MOV * T0.W, literal.x,
578 ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
579 ; EG-NEXT: BFE_UINT T1.W, KC0[4].X, literal.x, PV.W,
580 ; EG-NEXT: AND_INT * T2.W, KC0[4].X, literal.y,
581 ; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
582 ; EG-NEXT: OR_INT T0.Z, PS, literal.x,
583 ; EG-NEXT: BFE_UINT T2.W, KC0[3].Z, literal.y, T0.W,
584 ; EG-NEXT: ADD_INT * T3.W, PV.W, literal.z,
585 ; EG-NEXT: 8388608(1.175494e-38), 23(3.222986e-44)
586 ; EG-NEXT: -150(nan), 0(0.000000e+00)
587 ; EG-NEXT: ADD_INT T0.Y, PV.W, literal.x,
588 ; EG-NEXT: AND_INT T1.Z, PS, literal.y,
589 ; EG-NEXT: NOT_INT T4.W, PS,
590 ; EG-NEXT: LSHR * T5.W, PV.Z, 1,
591 ; EG-NEXT: -127(nan), 31(4.344025e-44)
592 ; EG-NEXT: ADD_INT T0.X, T1.W, literal.x,
593 ; EG-NEXT: BIT_ALIGN_INT T1.Y, 0.0, PS, PV.W,
594 ; EG-NEXT: AND_INT T2.Z, T3.W, literal.y, BS:VEC_201
595 ; EG-NEXT: LSHL T3.W, T0.Z, PV.Z,
596 ; EG-NEXT: SUB_INT * T1.W, literal.z, T1.W,
597 ; EG-NEXT: -127(nan), 32(4.484155e-44)
598 ; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
599 ; EG-NEXT: AND_INT T1.X, PS, literal.x,
600 ; EG-NEXT: BIT_ALIGN_INT T2.Y, 0.0, T0.Z, PS,
601 ; EG-NEXT: AND_INT T0.Z, KC0[3].Z, literal.y,
602 ; EG-NEXT: CNDE_INT T1.W, PV.Z, PV.Y, PV.W,
603 ; EG-NEXT: SETGT_INT * T4.W, PV.X, literal.z,
604 ; EG-NEXT: 32(4.484155e-44), 8388607(1.175494e-38)
605 ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
606 ; EG-NEXT: CNDE_INT T2.X, PS, 0.0, PV.W,
607 ; EG-NEXT: OR_INT T1.Y, PV.Z, literal.x,
608 ; EG-NEXT: ADD_INT T0.Z, T2.W, literal.y,
609 ; EG-NEXT: CNDE_INT T1.W, PV.X, PV.Y, 0.0,
610 ; EG-NEXT: CNDE_INT * T3.W, T2.Z, T3.W, 0.0,
611 ; EG-NEXT: 8388608(1.175494e-38), -150(nan)
612 ; EG-NEXT: CNDE_INT T1.X, T4.W, PV.W, PS,
613 ; EG-NEXT: ASHR T2.Y, KC0[4].X, literal.x,
614 ; EG-NEXT: AND_INT T1.Z, PV.Z, literal.x,
615 ; EG-NEXT: NOT_INT T1.W, PV.Z,
616 ; EG-NEXT: LSHR * T3.W, PV.Y, 1,
617 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
618 ; EG-NEXT: BIT_ALIGN_INT T3.X, 0.0, PS, PV.W,
619 ; EG-NEXT: LSHL T3.Y, T1.Y, PV.Z,
620 ; EG-NEXT: XOR_INT T1.Z, PV.X, PV.Y,
621 ; EG-NEXT: XOR_INT T1.W, T2.X, PV.Y,
622 ; EG-NEXT: SUB_INT * T2.W, literal.x, T2.W,
623 ; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
624 ; EG-NEXT: AND_INT T1.X, T0.Z, literal.x,
625 ; EG-NEXT: AND_INT T4.Y, PS, literal.x,
626 ; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, T1.Y, PS, BS:VEC_021/SCL_122
627 ; EG-NEXT: SUB_INT T1.W, PV.W, T2.Y,
628 ; EG-NEXT: SUBB_UINT * T2.W, PV.Z, T2.Y,
629 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
630 ; EG-NEXT: SUB_INT T2.X, PV.W, PS,
631 ; EG-NEXT: CNDE_INT T1.Y, PV.Y, PV.Z, 0.0,
632 ; EG-NEXT: CNDE_INT T0.Z, PV.X, T3.Y, 0.0,
633 ; EG-NEXT: CNDE_INT T1.W, PV.X, T3.X, T3.Y, BS:VEC_021/SCL_122
634 ; EG-NEXT: SETGT_INT * T2.W, T0.Y, literal.x,
635 ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
636 ; EG-NEXT: BFE_UINT T1.X, KC0[3].W, literal.x, T0.W,
637 ; EG-NEXT: AND_INT T3.Y, KC0[3].W, literal.y,
638 ; EG-NEXT: CNDE_INT T2.Z, PS, 0.0, PV.W,
639 ; EG-NEXT: CNDE_INT T1.W, PS, PV.Y, PV.Z,
640 ; EG-NEXT: ASHR * T2.W, KC0[3].Z, literal.z,
641 ; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
642 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
643 ; EG-NEXT: BFE_UINT T3.X, KC0[3].Y, literal.x, T0.W,
644 ; EG-NEXT: XOR_INT T1.Y, PV.W, PS,
645 ; EG-NEXT: XOR_INT T0.Z, PV.Z, PS,
646 ; EG-NEXT: OR_INT T0.W, PV.Y, literal.y,
647 ; EG-NEXT: SUB_INT * T1.W, literal.z, PV.X,
648 ; EG-NEXT: 23(3.222986e-44), 8388608(1.175494e-38)
649 ; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
650 ; EG-NEXT: AND_INT T4.X, KC0[3].Y, literal.x,
651 ; EG-NEXT: AND_INT T3.Y, PS, literal.y,
652 ; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PV.W, PS,
653 ; EG-NEXT: SUB_INT T1.W, PV.Z, T2.W,
654 ; EG-NEXT: SUBB_UINT * T3.W, PV.Y, T2.W,
655 ; EG-NEXT: 8388607(1.175494e-38), 32(4.484155e-44)
656 ; EG-NEXT: SUB_INT T5.X, PV.W, PS,
657 ; EG-NEXT: SETGT_INT T0.Y, 0.0, T0.Y,
658 ; EG-NEXT: CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,
659 ; EG-NEXT: OR_INT T1.W, PV.X, literal.x,
660 ; EG-NEXT: ADD_INT * T3.W, T3.X, literal.y,
661 ; EG-NEXT: 8388608(1.175494e-38), -150(nan)
662 ; EG-NEXT: ADD_INT T4.X, T3.X, literal.x,
663 ; EG-NEXT: SUB_INT T3.Y, literal.y, T3.X,
664 ; EG-NEXT: AND_INT T2.Z, PS, literal.z,
665 ; EG-NEXT: NOT_INT T4.W, PS,
666 ; EG-NEXT: LSHR * T5.W, PV.W, 1,
667 ; EG-NEXT: -127(nan), 150(2.101948e-43)
668 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
669 ; EG-NEXT: BIT_ALIGN_INT T3.X, 0.0, PS, PV.W,
670 ; EG-NEXT: LSHL T4.Y, T1.W, PV.Z,
671 ; EG-NEXT: AND_INT T2.Z, T3.W, literal.x, BS:VEC_120/SCL_212
672 ; EG-NEXT: BIT_ALIGN_INT T1.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122
673 ; EG-NEXT: AND_INT * T3.W, PV.Y, literal.x,
674 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
675 ; EG-NEXT: ADD_INT T6.X, T1.X, literal.x,
676 ; EG-NEXT: CNDE_INT T3.Y, PS, PV.W, 0.0,
677 ; EG-NEXT: CNDE_INT * T3.Z, PV.Z, PV.Y, 0.0,
678 ; EG-NEXT: -150(nan), 0(0.000000e+00)
679 ; EG-NEXT: ALU clause starting at 108:
680 ; EG-NEXT: CNDE_INT T1.W, T2.Z, T3.X, T4.Y,
681 ; EG-NEXT: SETGT_INT * T3.W, T4.X, literal.x,
682 ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
683 ; EG-NEXT: CNDE_INT T3.X, PS, 0.0, PV.W,
684 ; EG-NEXT: CNDE_INT T3.Y, PS, T3.Y, T3.Z,
685 ; EG-NEXT: AND_INT T2.Z, T6.X, literal.x,
686 ; EG-NEXT: NOT_INT T1.W, T6.X,
687 ; EG-NEXT: LSHR * T3.W, T0.W, 1,
688 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
689 ; EG-NEXT: ASHR T7.X, KC0[3].Y, literal.x,
690 ; EG-NEXT: ADD_INT T4.Y, T1.X, literal.y,
691 ; EG-NEXT: BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W,
692 ; EG-NEXT: LSHL T0.W, T0.W, PV.Z,
693 ; EG-NEXT: AND_INT * T1.W, T6.X, literal.z,
694 ; EG-NEXT: 31(4.344025e-44), -127(nan)
695 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
696 ; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0,
697 ; EG-NEXT: CNDE_INT T5.Y, PS, PV.Z, PV.W,
698 ; EG-NEXT: SETGT_INT T2.Z, PV.Y, literal.x,
699 ; EG-NEXT: XOR_INT T0.W, T3.Y, PV.X,
700 ; EG-NEXT: XOR_INT * T1.W, T3.X, PV.X,
701 ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
702 ; EG-NEXT: SUB_INT T3.X, PS, T7.X,
703 ; EG-NEXT: SUBB_UINT T3.Y, PV.W, T7.X,
704 ; EG-NEXT: CNDE_INT T3.Z, PV.Z, 0.0, PV.Y,
705 ; EG-NEXT: CNDE_INT T1.W, PV.Z, T0.Z, PV.X,
706 ; EG-NEXT: ASHR * T3.W, KC0[3].W, literal.x,
707 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
708 ; EG-NEXT: XOR_INT T1.X, PV.W, PS,
709 ; EG-NEXT: XOR_INT T5.Y, PV.Z, PS,
710 ; EG-NEXT: SUB_INT T0.Z, PV.X, PV.Y,
711 ; EG-NEXT: SETGT_INT T1.W, 0.0, T4.X, BS:VEC_021/SCL_122
712 ; EG-NEXT: CNDE_INT * T6.W, T0.Y, T5.X, 0.0,
713 ; EG-NEXT: SETGT_INT T0.X, 0.0, T0.X,
714 ; EG-NEXT: CNDE_INT T6.Y, PV.W, PV.Z, 0.0,
715 ; EG-NEXT: SUB_INT T0.Z, T1.Y, T2.W, BS:VEC_021/SCL_122
716 ; EG-NEXT: SUB_INT T2.W, PV.Y, T3.W,
717 ; EG-NEXT: SUBB_UINT * T4.W, PV.X, T3.W,
718 ; EG-NEXT: SUB_INT T3.X, PV.W, PS,
719 ; EG-NEXT: SETGT_INT T1.Y, 0.0, T4.Y,
720 ; EG-NEXT: CNDE_INT T6.Z, T0.Y, PV.Z, 0.0,
721 ; EG-NEXT: SUB_INT T0.W, T0.W, T7.X, BS:VEC_021/SCL_122
722 ; EG-NEXT: CNDE_INT * T4.W, PV.X, T2.X, 0.0,
723 ; EG-NEXT: CNDE_INT T6.X, T1.W, PV.W, 0.0,
724 ; EG-NEXT: CNDE_INT T4.Y, PV.Y, PV.X, 0.0,
725 ; EG-NEXT: SUB_INT T0.W, T1.Z, T2.Y,
726 ; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,
727 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
728 ; EG-NEXT: CNDE_INT T4.Z, T0.X, PV.W, 0.0,
729 ; EG-NEXT: SUB_INT * T0.W, T1.X, T3.W, BS:VEC_120/SCL_212
730 ; EG-NEXT: CNDE_INT T4.X, T1.Y, PV.W, 0.0,
731 ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
732 ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
733 ; EG-NEXT: LSHR * T0.X, PV.W, literal.x,
734 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
735 %conv = fptosi <4 x float> %x to <4 x i64>
736 store <4 x i64> %conv, ptr addrspace(1) %out
737 ret void
738 }
740 define amdgpu_kernel void @fp_to_uint_f32_to_i1(ptr addrspace(1) %out, float %in) #0 {
741 ; SI-LABEL: fp_to_uint_f32_to_i1:
742 ; SI: ; %bb.0:
743 ; SI-NEXT: s_load_dword s4, s[0:1], 0xb
744 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
745 ; SI-NEXT: s_mov_b32 s3, 0xf000
746 ; SI-NEXT: s_mov_b32 s2, -1
747 ; SI-NEXT: s_waitcnt lgkmcnt(0)
748 ; SI-NEXT: v_cmp_eq_f32_e64 s[4:5], -1.0, s4
749 ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
750 ; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0
751 ; SI-NEXT: s_endpgm
752 ;
753 ; VI-LABEL: fp_to_uint_f32_to_i1:
754 ; VI: ; %bb.0:
755 ; VI-NEXT: s_load_dword s4, s[0:1], 0x2c
756 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
757 ; VI-NEXT: s_mov_b32 s3, 0xf000
758 ; VI-NEXT: s_mov_b32 s2, -1
759 ; VI-NEXT: s_waitcnt lgkmcnt(0)
760 ; VI-NEXT: v_cmp_eq_f32_e64 s[4:5], -1.0, s4
761 ; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
762 ; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0
763 ; VI-NEXT: s_endpgm
764 ;
765 ; EG-LABEL: fp_to_uint_f32_to_i1:
766 ; EG: ; %bb.0:
767 ; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]
768 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
769 ; EG-NEXT: CF_END
770 ; EG-NEXT: PAD
771 ; EG-NEXT: ALU clause starting at 4:
772 ; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
773 ; EG-NEXT: SETE_DX10 * T1.W, KC0[2].Z, literal.y,
774 ; EG-NEXT: 3(4.203895e-45), -1082130432(-1.000000e+00)
775 ; EG-NEXT: AND_INT T1.W, PS, 1,
776 ; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
777 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
778 ; EG-NEXT: LSHL T0.X, PV.W, PS,
779 ; EG-NEXT: LSHL * T0.W, literal.x, PS,
780 ; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
781 ; EG-NEXT: MOV T0.Y, 0.0,
782 ; EG-NEXT: MOV * T0.Z, 0.0,
783 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
784 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
785 %conv = fptosi float %in to i1
786 store i1 %conv, ptr addrspace(1) %out
787 ret void
788 }
790 define amdgpu_kernel void @fp_to_uint_fabs_f32_to_i1(ptr addrspace(1) %out, float %in) #0 {
791 ; SI-LABEL: fp_to_uint_fabs_f32_to_i1:
792 ; SI: ; %bb.0:
793 ; SI-NEXT: s_load_dword s4, s[0:1], 0xb
794 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
795 ; SI-NEXT: s_mov_b32 s3, 0xf000
796 ; SI-NEXT: s_mov_b32 s2, -1
797 ; SI-NEXT: s_waitcnt lgkmcnt(0)
798 ; SI-NEXT: v_cmp_eq_f32_e64 s[4:5], -1.0, |s4|
799 ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
800 ; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0
801 ; SI-NEXT: s_endpgm
802 ;
803 ; VI-LABEL: fp_to_uint_fabs_f32_to_i1:
804 ; VI: ; %bb.0:
805 ; VI-NEXT: s_load_dword s4, s[0:1], 0x2c
806 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
807 ; VI-NEXT: s_mov_b32 s3, 0xf000
808 ; VI-NEXT: s_mov_b32 s2, -1
809 ; VI-NEXT: s_waitcnt lgkmcnt(0)
810 ; VI-NEXT: v_cmp_eq_f32_e64 s[4:5], -1.0, |s4|
811 ; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
812 ; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0
813 ; VI-NEXT: s_endpgm
814 ;
815 ; EG-LABEL: fp_to_uint_fabs_f32_to_i1:
816 ; EG: ; %bb.0:
817 ; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]
818 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
819 ; EG-NEXT: CF_END
820 ; EG-NEXT: PAD
821 ; EG-NEXT: ALU clause starting at 4:
822 ; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
823 ; EG-NEXT: SETE_DX10 * T1.W, |KC0[2].Z|, literal.y,
824 ; EG-NEXT: 3(4.203895e-45), -1082130432(-1.000000e+00)
825 ; EG-NEXT: AND_INT T1.W, PS, 1,
826 ; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
827 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
828 ; EG-NEXT: LSHL T0.X, PV.W, PS,
829 ; EG-NEXT: LSHL * T0.W, literal.x, PS,
830 ; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
831 ; EG-NEXT: MOV T0.Y, 0.0,
832 ; EG-NEXT: MOV * T0.Z, 0.0,
833 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
834 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
835 %in.fabs = call float @llvm.fabs.f32(float %in)
836 %conv = fptosi float %in.fabs to i1
837 store i1 %conv, ptr addrspace(1) %out
838 ret void
839 }
841 define amdgpu_kernel void @fp_to_sint_f32_i16(ptr addrspace(1) %out, float %in) #0 {
842 ; SI-LABEL: fp_to_sint_f32_i16:
843 ; SI: ; %bb.0:
844 ; SI-NEXT: s_load_dword s4, s[0:1], 0xb
845 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
846 ; SI-NEXT: s_mov_b32 s3, 0xf000
847 ; SI-NEXT: s_mov_b32 s2, -1
848 ; SI-NEXT: s_waitcnt lgkmcnt(0)
849 ; SI-NEXT: v_cvt_i32_f32_e32 v0, s4
850 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
851 ; SI-NEXT: s_endpgm
852 ;
853 ; VI-LABEL: fp_to_sint_f32_i16:
854 ; VI: ; %bb.0:
855 ; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
856 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
857 ; VI-NEXT: s_mov_b32 s3, 0xf000
858 ; VI-NEXT: s_waitcnt lgkmcnt(0)
859 ; VI-NEXT: v_cvt_i32_f32_e32 v0, s2
860 ; VI-NEXT: s_mov_b32 s2, -1
861 ; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
862 ; VI-NEXT: s_endpgm
863 ;
864 ; EG-LABEL: fp_to_sint_f32_i16:
865 ; EG: ; %bb.0:
866 ; EG-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]
867 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
868 ; EG-NEXT: CF_END
869 ; EG-NEXT: PAD
870 ; EG-NEXT: ALU clause starting at 4:
871 ; EG-NEXT: TRUNC T0.W, KC0[2].Z,
872 ; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
873 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
874 ; EG-NEXT: FLT_TO_INT * T0.W, PV.W,
875 ; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
876 ; EG-NEXT: LSHL * T1.W, T1.W, literal.y,
877 ; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)
878 ; EG-NEXT: LSHL T0.X, PV.W, PS,
879 ; EG-NEXT: LSHL * T0.W, literal.x, PS,
880 ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
881 ; EG-NEXT: MOV T0.Y, 0.0,
882 ; EG-NEXT: MOV * T0.Z, 0.0,
883 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
884 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
885 %sint = fptosi float %in to i16
886 store i16 %sint, ptr addrspace(1) %out
887 ret void
888 }
890 attributes #0 = { nounwind }
891 attributes #1 = { nounwind readnone }